artix7: Updating the harnesses.
* Arty-A7
- pmod
- swbut
- uart
* Basys3
- swbut
Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/Info.md b/Info.md
index 2398b36..9f57772 100644
--- a/Info.md
+++ b/Info.md
@@ -37,7 +37,7 @@
# Details
-Last updated on Tue Mar 26 20:43:13 UTC 2019 (2019-03-26T20:43:13+00:00).
+Last updated on Wed Mar 27 01:22:23 UTC 2019 (2019-03-27T01:22:23+00:00).
Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [c7d7e9d](https://github.com/SymbiFlow/prjxray/commit/c7d7e9d7ade70bd47f969f9713d9a6e4defbd53a).
@@ -97,21 +97,21 @@
* [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv)
* [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt)
* [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md)
- * [`8416e8eef29e5defebbd3e45f60baa15cbcc22d66647a8da62ec7c42eff8b521 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
- * [`c98eefb677a5cd469b75223d6ceb0e95f5d331de00291193caed008f33ee746c ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
- * [`13382ee7fffcd88636892517929e7c60a6e82bb63324a4e48414bb16eb81174b ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
- * [`0c0db34e2b1a0f38b05799ad7e042874d43443d79426e9f32f0b63c71a8c9d3d ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
- * [`0df8a22d29a4425ee1da4363b8cdb56c82c1ab71913fbe36b4470b3ebc082c60 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
- * [`578bbe948ecc1af59c3e9cda0aacd53841d31534a6ec156af9d2779aee8770f4 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
- * [`124264a1ac88ce1e72eef3d337dc1b67287413036e1e0bf4e1eb52df3cef17ee ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
- * [`d8c1255df5bc352fbff05b9688b86becfc7d28ee82663256332e0a7b8ac4b338 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
- * [`7f92af7280a5e8563dd764c52356e2f914a20b5d413ff1441c546da6101df21c ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
- * [`78616f1443dcacb0af37f78ba507c81f0a6115770e538430d5c7382aa48edd6a ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
- * [`8df57ddc871785ba1710beb4a14c6ceed706cfb48bfbc425182f2a96742fdd13 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
+ * [`b270ca64ce9a15a0a2cde99523bab6e7ba748fbca804dd600ccb2c21a4224c85 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit)
+ * [`134f6438b4dbbd511c823e80548970359e9468b2509e6614732ef2d591613c53 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp)
+ * [`39236ffb06698077ee3f06edd6d64c0167793cefab4acda71f219a5cf3a20f76 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json)
+ * [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt)
+ * [`5e4504596aaca26baf85309f7e223a9e45af410971af8c21b375f8151e9e6a53 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit)
+ * [`6c20fcdb578030f58da1082539828d2785065a598f8ca9c2d14b49d3a6ebe834 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp)
+ * [`63af3a7ba401751dc4b03cd2db38d5a4c6d20279117307138fee3fcb92ab1119 ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json)
+ * [`7d2429e6bcedecaf6f0db4f2f04860b5b6dc4b036495815a70edc4a036361310 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt)
+ * [`e492a4c97f0d0a10cd07e0badb0b81f084e2d1a88ba06ab5b705e90ef6003076 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit)
+ * [`e2dbcf498c7efe26d6a4ab14733bf3acfe51798bc1d2cd7f4e0e77fc95f40225 ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp)
+ * [`62586079b9ffd917ff5a5d4edcae802b161a7ed4f6af1c776731dcd10c87d096 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json)
* [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt)
- * [`3e70378bc05fe32951fed4816f634ff35e5f1511d992ebf8e6718d6d8a65943f ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
- * [`8cac3f210fcc33e78fe576841c286a19138be26004dee70397f93a0b3019e451 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
- * [`2e19b7f8aaaf6fd6e891fa16ceb351eaf659202ef512598ec8f518c57d6ab484 ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
+ * [`4f590875a7851c6d036ab171421b12100f517af74229ad47d8e21fdb6e09b09e ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
+ * [`0e48014931ae9a6010d6023b2a6e07e13ecf206be1076197b881161e67ced596 ./artix7/harness/basys3/swbut/design.dcp`](./artix7/harness/basys3/swbut/design.dcp)
+ * [`9bc42fedabb2f8ca69d0431b5e9c22f20c09b8fa5313dd252d0c32c32b6ad80b ./artix7/harness/basys3/swbut/design.json`](./artix7/harness/basys3/swbut/design.json)
* [`9df8eac3c11e57d81b4bf4a927ade787f881f0ef46c8ab610ca529f35e887689 ./artix7/harness/basys3/swbut/design.txt`](./artix7/harness/basys3/swbut/design.txt)
* [`fca753747fb1d583483e22980c4dae3a2de6451a326d46eab3581ea6f50f5b2d ./artix7/mask_bram_l.block_ram.db`](./artix7/mask_bram_l.block_ram.db)
* [`30b4cfe8b60ccde4423a0bd0d7ad5242bea58d54abf5d15601dd3f390465e821 ./artix7/mask_bram_l.db`](./artix7/mask_bram_l.db)
diff --git a/artix7/harness/arty-a7/pmod/design.bit b/artix7/harness/arty-a7/pmod/design.bit
index 462374a..f69a3de 100644
--- a/artix7/harness/arty-a7/pmod/design.bit
+++ b/artix7/harness/arty-a7/pmod/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/pmod/design.dcp b/artix7/harness/arty-a7/pmod/design.dcp
index d26c67e..3977d16 100644
--- a/artix7/harness/arty-a7/pmod/design.dcp
+++ b/artix7/harness/arty-a7/pmod/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/pmod/design.json b/artix7/harness/arty-a7/pmod/design.json
index 1bcc700..cdbcec2 100644
--- a/artix7/harness/arty-a7/pmod/design.json
+++ b/artix7/harness/arty-a7/pmod/design.json
@@ -1,8 +1,8 @@
{
"info": {
- "GRID_X_MAX": 47,
- "GRID_X_MIN": 18,
- "GRID_Y_MAX": 52,
+ "GRID_X_MAX": 58,
+ "GRID_X_MIN": 10,
+ "GRID_Y_MAX": 51,
"GRID_Y_MIN": 0
},
"ports": [
@@ -14,99 +14,1153 @@
},
{
"name": "din[0]",
- "node": "INT_R_X9Y102/NE2BEG3",
+ "node": "INT_L_X0Y102/EE2BEG2",
"pin": "E15",
- "wire": "VBRK_X29Y108/VBRK_NE2A3"
+ "wire": "VBRK_X9Y107/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV15",
+ "BRKH_INT_X0Y99/BRKH_INT_NN6C2",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2",
+ "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LV_L16",
+ "INT_L_X0Y100/NN6D2",
+ "INT_L_X0Y101/LV_L17",
+ "INT_L_X0Y101/NN6E2",
+ "INT_L_X0Y102/EE2BEG2",
+ "INT_L_X0Y102/LV_L18",
+ "INT_L_X0Y102/NN6END2",
+ "INT_L_X0Y78/LOGIC_OUTS_L18",
+ "INT_L_X0Y78/NN6BEG0",
+ "INT_L_X0Y79/NN6A0",
+ "INT_L_X0Y80/NN6B0",
+ "INT_L_X0Y81/NN6C0",
+ "INT_L_X0Y82/NN6D0",
+ "INT_L_X0Y83/NN6E0",
+ "INT_L_X0Y83/NN6END_S1_0",
+ "INT_L_X0Y84/LVB_L0",
+ "INT_L_X0Y84/LV_L0",
+ "INT_L_X0Y84/NN6END0",
+ "INT_L_X0Y85/LVB_L1",
+ "INT_L_X0Y85/LV_L1",
+ "INT_L_X0Y86/LVB_L2",
+ "INT_L_X0Y86/LV_L2",
+ "INT_L_X0Y87/LVB_L3",
+ "INT_L_X0Y87/LV_L3",
+ "INT_L_X0Y88/LVB_L4",
+ "INT_L_X0Y88/LV_L4",
+ "INT_L_X0Y89/LVB_L5",
+ "INT_L_X0Y89/LV_L5",
+ "INT_L_X0Y90/LVB_L6",
+ "INT_L_X0Y90/LV_L6",
+ "INT_L_X0Y91/LVB_L7",
+ "INT_L_X0Y91/LV_L7",
+ "INT_L_X0Y92/LVB_L8",
+ "INT_L_X0Y92/LV_L8",
+ "INT_L_X0Y93/LVB_L9",
+ "INT_L_X0Y93/LV_L9",
+ "INT_L_X0Y94/LVB_L10",
+ "INT_L_X0Y94/LV_L10",
+ "INT_L_X0Y95/LVB_L11",
+ "INT_L_X0Y95/LV_L11",
+ "INT_L_X0Y96/LVB_L12",
+ "INT_L_X0Y96/LV_L12",
+ "INT_L_X0Y96/NN6BEG2",
+ "INT_L_X0Y97/LV_L13",
+ "INT_L_X0Y97/NN6A2",
+ "INT_L_X0Y98/LV_L14",
+ "INT_L_X0Y98/NN6B2",
+ "INT_L_X0Y99/LV_L15",
+ "INT_L_X0Y99/NN6C2",
+ "INT_R_X1Y102/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y78/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y78/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y77/IOB_IBUF0",
+ "LIOI3_X0Y77/IOI_ILOGIC0_O",
+ "LIOI3_X0Y77/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y77/LIOI_I0",
+ "LIOI3_X0Y77/LIOI_IBUF0",
+ "LIOI3_X0Y77/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y82/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y107/VBRK_EE2A2"
+ ]
},
{
"name": "din[1]",
- "node": "INT_R_X9Y105/NE2BEG3",
+ "node": "INT_L_X0Y104/EE2BEG2",
"pin": "E16",
- "wire": "VBRK_X29Y111/VBRK_NE2A3"
+ "wire": "VBRK_X9Y109/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV16",
+ "BRKH_INT_X0Y99/BRKH_INT_NN6A1",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4",
+ "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LV_L17",
+ "INT_L_X0Y100/NN6B1",
+ "INT_L_X0Y101/LV_L18",
+ "INT_L_X0Y101/NN6C1",
+ "INT_L_X0Y102/NN6D1",
+ "INT_L_X0Y103/NN6E1",
+ "INT_L_X0Y104/EE2BEG2",
+ "INT_L_X0Y104/ER1END2",
+ "INT_L_X0Y104/NN6END1",
+ "INT_L_X0Y104/WR1BEG2",
+ "INT_L_X0Y77/LOGIC_OUTS_L18",
+ "INT_L_X0Y77/NN6BEG0",
+ "INT_L_X0Y78/NN6A0",
+ "INT_L_X0Y79/NN6B0",
+ "INT_L_X0Y80/NN6C0",
+ "INT_L_X0Y81/NN6D0",
+ "INT_L_X0Y82/NN6E0",
+ "INT_L_X0Y82/NN6END_S1_0",
+ "INT_L_X0Y83/LV_L0",
+ "INT_L_X0Y83/NN6END0",
+ "INT_L_X0Y84/LV_L1",
+ "INT_L_X0Y85/LV_L2",
+ "INT_L_X0Y86/LV_L3",
+ "INT_L_X0Y87/LV_L4",
+ "INT_L_X0Y88/LV_L5",
+ "INT_L_X0Y89/LV_L6",
+ "INT_L_X0Y90/LV_L7",
+ "INT_L_X0Y91/LV_L8",
+ "INT_L_X0Y92/LV_L9",
+ "INT_L_X0Y92/NN6BEG1",
+ "INT_L_X0Y93/LV_L10",
+ "INT_L_X0Y93/NN6A1",
+ "INT_L_X0Y94/LV_L11",
+ "INT_L_X0Y94/NN6B1",
+ "INT_L_X0Y95/LV_L12",
+ "INT_L_X0Y95/NN6C1",
+ "INT_L_X0Y96/LV_L13",
+ "INT_L_X0Y96/NN6D1",
+ "INT_L_X0Y97/LV_L14",
+ "INT_L_X0Y97/NN6E1",
+ "INT_L_X0Y98/LV_L15",
+ "INT_L_X0Y98/NN6BEG1",
+ "INT_L_X0Y98/NN6END1",
+ "INT_L_X0Y99/LV_L16",
+ "INT_L_X0Y99/NN6A1",
+ "INT_R_X1Y104/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_ER1BEG2",
+ "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_WR1END2",
+ "IO_INT_INTERFACE_L_X0Y77/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y77/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y77/IOB_IBUF1",
+ "LIOI3_X0Y77/IOI_ILOGIC1_O",
+ "LIOI3_X0Y77/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y77/LIOI_I1",
+ "LIOI3_X0Y77/LIOI_IBUF1",
+ "LIOI3_X0Y77/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y109/L_TERM_INT_WR1BEG3",
+ "L_TERM_INT_X2Y81/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y109/VBRK_EE2A2"
+ ]
},
{
"name": "din[2]",
- "node": "INT_R_X9Y108/NE2BEG3",
+ "node": "INT_L_X0Y106/EE2BEG2",
"pin": "D15",
- "wire": "VBRK_X29Y114/VBRK_NE2A3"
+ "wire": "VBRK_X9Y111/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV17",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6",
+ "INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LVB_L0",
+ "INT_L_X0Y100/LV_L18",
+ "INT_L_X0Y101/LVB_L1",
+ "INT_L_X0Y102/LVB_L2",
+ "INT_L_X0Y103/LVB_L3",
+ "INT_L_X0Y104/LVB_L4",
+ "INT_L_X0Y105/LVB_L5",
+ "INT_L_X0Y106/EE2BEG2",
+ "INT_L_X0Y106/LVB_L6",
+ "INT_L_X0Y106/SS6END2",
+ "INT_L_X0Y107/LVB_L7",
+ "INT_L_X0Y107/SS6E2",
+ "INT_L_X0Y108/LVB_L8",
+ "INT_L_X0Y108/SS6D2",
+ "INT_L_X0Y109/LVB_L9",
+ "INT_L_X0Y109/SS6C2",
+ "INT_L_X0Y110/LVB_L10",
+ "INT_L_X0Y110/SS6B2",
+ "INT_L_X0Y111/LVB_L11",
+ "INT_L_X0Y111/SS6A2",
+ "INT_L_X0Y112/LVB_L12",
+ "INT_L_X0Y112/SS6BEG2",
+ "INT_L_X0Y76/LOGIC_OUTS_L18",
+ "INT_L_X0Y76/NN6BEG0",
+ "INT_L_X0Y77/NN6A0",
+ "INT_L_X0Y78/NN6B0",
+ "INT_L_X0Y79/NN6C0",
+ "INT_L_X0Y80/NN6D0",
+ "INT_L_X0Y81/NN6E0",
+ "INT_L_X0Y81/NN6END_S1_0",
+ "INT_L_X0Y82/LV_L0",
+ "INT_L_X0Y82/NN6END0",
+ "INT_L_X0Y83/LV_L1",
+ "INT_L_X0Y84/LV_L2",
+ "INT_L_X0Y85/LV_L3",
+ "INT_L_X0Y86/LV_L4",
+ "INT_L_X0Y87/LV_L5",
+ "INT_L_X0Y88/LV_L6",
+ "INT_L_X0Y89/LV_L7",
+ "INT_L_X0Y90/LV_L8",
+ "INT_L_X0Y91/LV_L9",
+ "INT_L_X0Y92/LV_L10",
+ "INT_L_X0Y93/LV_L11",
+ "INT_L_X0Y94/LV_L12",
+ "INT_L_X0Y95/LV_L13",
+ "INT_L_X0Y96/LV_L14",
+ "INT_L_X0Y97/LV_L15",
+ "INT_L_X0Y98/LV_L16",
+ "INT_L_X0Y99/LV_L17",
+ "INT_R_X1Y106/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y76/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y76/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y75/IOB_IBUF0",
+ "LIOI3_X0Y75/IOI_ILOGIC0_O",
+ "LIOI3_X0Y75/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y75/LIOI_I0",
+ "LIOI3_X0Y75/LIOI_IBUF0",
+ "LIOI3_X0Y75/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y80/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y111/VBRK_EE2A2"
+ ]
},
{
"name": "din[3]",
- "node": "INT_R_X9Y111/NE2BEG3",
+ "node": "INT_L_X0Y108/EE2BEG2",
"pin": "C15",
- "wire": "VBRK_X29Y117/VBRK_NE2A3"
+ "wire": "VBRK_X9Y113/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_NN6BEG3",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8",
+ "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/NN6A3",
+ "INT_L_X0Y101/NN6B3",
+ "INT_L_X0Y102/NN6C3",
+ "INT_L_X0Y103/NN6D3",
+ "INT_L_X0Y104/NN6E3",
+ "INT_L_X0Y105/NN2BEG3",
+ "INT_L_X0Y105/NN6END3",
+ "INT_L_X0Y106/NN2A3",
+ "INT_L_X0Y107/NL1BEG2",
+ "INT_L_X0Y107/NN2END3",
+ "INT_L_X0Y108/EE2BEG2",
+ "INT_L_X0Y108/NL1END2",
+ "INT_L_X0Y75/LOGIC_OUTS_L18",
+ "INT_L_X0Y75/NN6BEG0",
+ "INT_L_X0Y76/NN6A0",
+ "INT_L_X0Y77/NN6B0",
+ "INT_L_X0Y78/NN6C0",
+ "INT_L_X0Y79/NN6D0",
+ "INT_L_X0Y80/NN6E0",
+ "INT_L_X0Y80/NN6END_S1_0",
+ "INT_L_X0Y81/LV_L0",
+ "INT_L_X0Y81/NN6END0",
+ "INT_L_X0Y82/LV_L1",
+ "INT_L_X0Y83/LV_L2",
+ "INT_L_X0Y84/LV_L3",
+ "INT_L_X0Y85/LV_L4",
+ "INT_L_X0Y86/LV_L5",
+ "INT_L_X0Y87/LV_L6",
+ "INT_L_X0Y88/LV_L7",
+ "INT_L_X0Y89/LV_L8",
+ "INT_L_X0Y90/LV_L9",
+ "INT_L_X0Y91/LV_L10",
+ "INT_L_X0Y92/LV_L11",
+ "INT_L_X0Y93/LV_L12",
+ "INT_L_X0Y94/LV_L13",
+ "INT_L_X0Y95/LV_L14",
+ "INT_L_X0Y96/LV_L15",
+ "INT_L_X0Y97/LV_L16",
+ "INT_L_X0Y98/LV_L17",
+ "INT_L_X0Y99/LV_L18",
+ "INT_L_X0Y99/NN6BEG3",
+ "INT_R_X1Y108/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y75/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y75/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y75/IOB_IBUF1",
+ "LIOI3_X0Y75/IOI_ILOGIC1_O",
+ "LIOI3_X0Y75/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y75/LIOI_I1",
+ "LIOI3_X0Y75/LIOI_IBUF1",
+ "LIOI3_X0Y75/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y79/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y113/VBRK_EE2A2"
+ ]
},
{
"name": "din[4]",
- "node": "INT_R_X9Y114/NE2BEG3",
+ "node": "INT_L_X0Y110/EE2BEG2",
"pin": "J17",
- "wire": "VBRK_X29Y120/VBRK_NE2A3"
+ "wire": "VBRK_X9Y115/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_LVB_L9",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10",
+ "HCLK_L_X4Y78/HCLK_LV1",
+ "INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LVB_L9",
+ "INT_L_X0Y101/LVB_L10",
+ "INT_L_X0Y102/LVB_L11",
+ "INT_L_X0Y103/LVB_L12",
+ "INT_L_X0Y103/NN6BEG2",
+ "INT_L_X0Y104/NN6A2",
+ "INT_L_X0Y105/NN6B2",
+ "INT_L_X0Y106/NN6C2",
+ "INT_L_X0Y107/NN6D2",
+ "INT_L_X0Y108/NN6E2",
+ "INT_L_X0Y109/NN6END2",
+ "INT_L_X0Y109/NR1BEG2",
+ "INT_L_X0Y110/EE2BEG2",
+ "INT_L_X0Y110/NR1END2",
+ "INT_L_X0Y54/LOGIC_OUTS_L18",
+ "INT_L_X0Y54/NR1BEG0",
+ "INT_L_X0Y55/LV_L0",
+ "INT_L_X0Y55/NR1END0",
+ "INT_L_X0Y56/LV_L1",
+ "INT_L_X0Y57/LV_L2",
+ "INT_L_X0Y58/LV_L3",
+ "INT_L_X0Y59/LV_L4",
+ "INT_L_X0Y60/LV_L5",
+ "INT_L_X0Y61/LV_L6",
+ "INT_L_X0Y62/LV_L7",
+ "INT_L_X0Y63/LV_L8",
+ "INT_L_X0Y64/LV_L9",
+ "INT_L_X0Y65/LV_L10",
+ "INT_L_X0Y66/LV_L11",
+ "INT_L_X0Y67/LV_L12",
+ "INT_L_X0Y68/LV_L13",
+ "INT_L_X0Y69/LV_L14",
+ "INT_L_X0Y70/LV_L15",
+ "INT_L_X0Y71/LV_L16",
+ "INT_L_X0Y72/LV_L17",
+ "INT_L_X0Y73/LV_L0",
+ "INT_L_X0Y73/LV_L18",
+ "INT_L_X0Y74/LV_L1",
+ "INT_L_X0Y75/LV_L2",
+ "INT_L_X0Y76/LV_L3",
+ "INT_L_X0Y77/LV_L4",
+ "INT_L_X0Y78/LV_L5",
+ "INT_L_X0Y79/LV_L6",
+ "INT_L_X0Y80/LV_L7",
+ "INT_L_X0Y81/LV_L8",
+ "INT_L_X0Y82/LV_L9",
+ "INT_L_X0Y83/LV_L10",
+ "INT_L_X0Y84/LV_L11",
+ "INT_L_X0Y85/LV_L12",
+ "INT_L_X0Y86/LV_L13",
+ "INT_L_X0Y87/LV_L14",
+ "INT_L_X0Y88/LV_L15",
+ "INT_L_X0Y89/LV_L16",
+ "INT_L_X0Y90/LV_L17",
+ "INT_L_X0Y91/LVB_L0",
+ "INT_L_X0Y91/LV_L18",
+ "INT_L_X0Y92/LVB_L1",
+ "INT_L_X0Y93/LVB_L2",
+ "INT_L_X0Y94/LVB_L3",
+ "INT_L_X0Y95/LVB_L4",
+ "INT_L_X0Y96/LVB_L5",
+ "INT_L_X0Y97/LVB_L6",
+ "INT_L_X0Y98/LVB_L7",
+ "INT_L_X0Y99/LVB_L8",
+ "INT_R_X1Y110/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y54/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y54/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y53/IOB_IBUF0",
+ "LIOI3_X0Y53/IOI_ILOGIC0_O",
+ "LIOI3_X0Y53/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y53/LIOI_I0",
+ "LIOI3_X0Y53/LIOI_IBUF0",
+ "LIOI3_X0Y53/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y57/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y115/VBRK_EE2A2"
+ ]
},
{
"name": "din[5]",
- "node": "INT_R_X9Y117/NE2BEG3",
+ "node": "INT_L_X0Y112/EE2BEG2",
"pin": "J18",
- "wire": "VBRK_X29Y123/VBRK_NE2A3"
+ "wire": "VBRK_X9Y117/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV9",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12",
+ "HCLK_L_X4Y78/HCLK_LV2",
+ "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LV_L10",
+ "INT_L_X0Y101/LV_L11",
+ "INT_L_X0Y102/LV_L12",
+ "INT_L_X0Y103/LV_L13",
+ "INT_L_X0Y104/LV_L14",
+ "INT_L_X0Y105/LV_L15",
+ "INT_L_X0Y106/LV_L16",
+ "INT_L_X0Y107/LV_L17",
+ "INT_L_X0Y108/LV_L18",
+ "INT_L_X0Y108/NE6A3",
+ "INT_L_X0Y108/NW6BEG3",
+ "INT_L_X0Y109/NE6B3",
+ "INT_L_X0Y110/NE6C3",
+ "INT_L_X0Y111/NE6D3",
+ "INT_L_X0Y112/EE2BEG2",
+ "INT_L_X0Y112/EL1END2",
+ "INT_L_X0Y112/NE6E3",
+ "INT_L_X0Y112/WL1BEG2",
+ "INT_L_X0Y112/WR1END_S1_0",
+ "INT_L_X0Y113/WR1END0",
+ "INT_L_X0Y53/LOGIC_OUTS_L18",
+ "INT_L_X0Y53/NR1BEG0",
+ "INT_L_X0Y54/LV_L0",
+ "INT_L_X0Y54/NR1END0",
+ "INT_L_X0Y55/LV_L1",
+ "INT_L_X0Y56/LV_L2",
+ "INT_L_X0Y57/LV_L3",
+ "INT_L_X0Y58/LV_L4",
+ "INT_L_X0Y59/LV_L5",
+ "INT_L_X0Y60/LV_L6",
+ "INT_L_X0Y61/LV_L7",
+ "INT_L_X0Y62/LV_L8",
+ "INT_L_X0Y63/LV_L9",
+ "INT_L_X0Y64/LV_L10",
+ "INT_L_X0Y65/LV_L11",
+ "INT_L_X0Y66/LV_L12",
+ "INT_L_X0Y67/LV_L13",
+ "INT_L_X0Y68/LV_L14",
+ "INT_L_X0Y69/LV_L15",
+ "INT_L_X0Y70/LV_L16",
+ "INT_L_X0Y71/LV_L17",
+ "INT_L_X0Y72/LV_L0",
+ "INT_L_X0Y72/LV_L18",
+ "INT_L_X0Y73/LV_L1",
+ "INT_L_X0Y74/LV_L2",
+ "INT_L_X0Y75/LV_L3",
+ "INT_L_X0Y76/LV_L4",
+ "INT_L_X0Y77/LV_L5",
+ "INT_L_X0Y78/LV_L6",
+ "INT_L_X0Y79/LV_L7",
+ "INT_L_X0Y80/LV_L8",
+ "INT_L_X0Y81/LV_L9",
+ "INT_L_X0Y82/LV_L10",
+ "INT_L_X0Y83/LV_L11",
+ "INT_L_X0Y84/LV_L12",
+ "INT_L_X0Y85/LV_L13",
+ "INT_L_X0Y86/LV_L14",
+ "INT_L_X0Y87/LV_L15",
+ "INT_L_X0Y88/LV_L16",
+ "INT_L_X0Y89/LV_L17",
+ "INT_L_X0Y90/LV_L0",
+ "INT_L_X0Y90/LV_L18",
+ "INT_L_X0Y91/LV_L1",
+ "INT_L_X0Y92/LV_L2",
+ "INT_L_X0Y93/LV_L3",
+ "INT_L_X0Y94/LV_L4",
+ "INT_L_X0Y95/LV_L5",
+ "INT_L_X0Y96/LV_L6",
+ "INT_L_X0Y97/LV_L7",
+ "INT_L_X0Y98/LV_L8",
+ "INT_L_X0Y99/LV_L9",
+ "INT_R_X1Y112/EE2A2",
+ "INT_R_X1Y112/NE6END3",
+ "INT_R_X1Y112/WR1BEG_S0",
+ "INT_R_X1Y113/WR1BEG0",
+ "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_NE4BEG3",
+ "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_NW4A3",
+ "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_EL1BEG2",
+ "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_WL1END2",
+ "IO_INT_INTERFACE_L_X0Y53/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y53/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y53/IOB_IBUF1",
+ "LIOI3_X0Y53/IOI_ILOGIC1_O",
+ "LIOI3_X0Y53/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y53/LIOI_I1",
+ "LIOI3_X0Y53/LIOI_IBUF1",
+ "LIOI3_X0Y53/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y113/L_TERM_INT_NW4BEG3",
+ "L_TERM_INT_X2Y117/L_TERM_INT_WL1BEG2",
+ "L_TERM_INT_X2Y56/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y117/VBRK_EE2A2"
+ ]
},
{
"name": "din[6]",
- "node": "INT_R_X9Y120/NE2BEG3",
+ "node": "INT_L_X0Y114/EE2BEG2",
"pin": "K15",
- "wire": "VBRK_X29Y126/VBRK_NE2A3"
+ "wire": "VBRK_X9Y119/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV10",
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14",
+ "HCLK_L_X4Y78/HCLK_LV3",
+ "INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LV_L11",
+ "INT_L_X0Y101/LV_L12",
+ "INT_L_X0Y102/LV_L13",
+ "INT_L_X0Y103/LV_L14",
+ "INT_L_X0Y104/LV_L15",
+ "INT_L_X0Y105/LV_L16",
+ "INT_L_X0Y106/LV_L17",
+ "INT_L_X0Y107/LV_L18",
+ "INT_L_X0Y107/NN6BEG3",
+ "INT_L_X0Y108/NN6A3",
+ "INT_L_X0Y109/NN6B3",
+ "INT_L_X0Y110/NN6C3",
+ "INT_L_X0Y111/NN6D3",
+ "INT_L_X0Y112/NN6E3",
+ "INT_L_X0Y113/NL1BEG2",
+ "INT_L_X0Y113/NN6END3",
+ "INT_L_X0Y114/EE2BEG2",
+ "INT_L_X0Y114/NL1END2",
+ "INT_L_X0Y52/LOGIC_OUTS_L18",
+ "INT_L_X0Y52/NR1BEG0",
+ "INT_L_X0Y53/LV_L0",
+ "INT_L_X0Y53/NR1END0",
+ "INT_L_X0Y54/LV_L1",
+ "INT_L_X0Y55/LV_L2",
+ "INT_L_X0Y56/LV_L3",
+ "INT_L_X0Y57/LV_L4",
+ "INT_L_X0Y58/LV_L5",
+ "INT_L_X0Y59/LV_L6",
+ "INT_L_X0Y60/LV_L7",
+ "INT_L_X0Y61/LV_L8",
+ "INT_L_X0Y62/LV_L9",
+ "INT_L_X0Y63/LV_L10",
+ "INT_L_X0Y64/LV_L11",
+ "INT_L_X0Y65/LV_L12",
+ "INT_L_X0Y66/LV_L13",
+ "INT_L_X0Y67/LV_L14",
+ "INT_L_X0Y68/LV_L15",
+ "INT_L_X0Y69/LV_L16",
+ "INT_L_X0Y70/LV_L17",
+ "INT_L_X0Y71/LV_L0",
+ "INT_L_X0Y71/LV_L18",
+ "INT_L_X0Y72/LV_L1",
+ "INT_L_X0Y73/LV_L2",
+ "INT_L_X0Y74/LV_L3",
+ "INT_L_X0Y75/LV_L4",
+ "INT_L_X0Y76/LV_L5",
+ "INT_L_X0Y77/LV_L6",
+ "INT_L_X0Y78/LV_L7",
+ "INT_L_X0Y79/LV_L8",
+ "INT_L_X0Y80/LV_L9",
+ "INT_L_X0Y81/LV_L10",
+ "INT_L_X0Y82/LV_L11",
+ "INT_L_X0Y83/LV_L12",
+ "INT_L_X0Y84/LV_L13",
+ "INT_L_X0Y85/LV_L14",
+ "INT_L_X0Y86/LV_L15",
+ "INT_L_X0Y87/LV_L16",
+ "INT_L_X0Y88/LV_L17",
+ "INT_L_X0Y89/LV_L0",
+ "INT_L_X0Y89/LV_L18",
+ "INT_L_X0Y90/LV_L1",
+ "INT_L_X0Y91/LV_L2",
+ "INT_L_X0Y92/LV_L3",
+ "INT_L_X0Y93/LV_L4",
+ "INT_L_X0Y94/LV_L5",
+ "INT_L_X0Y95/LV_L6",
+ "INT_L_X0Y96/LV_L7",
+ "INT_L_X0Y97/LV_L8",
+ "INT_L_X0Y98/LV_L9",
+ "INT_L_X0Y99/LV_L10",
+ "INT_R_X1Y114/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y52/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y52/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y51/IOB_IBUF0",
+ "LIOI3_X0Y51/IOI_ILOGIC0_O",
+ "LIOI3_X0Y51/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y51/LIOI_I0",
+ "LIOI3_X0Y51/LIOI_IBUF0",
+ "LIOI3_X0Y51/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y55/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y119/VBRK_EE2A2"
+ ]
},
{
"name": "din[7]",
- "node": "INT_R_X9Y123/NE2BEG3",
+ "node": "INT_L_X0Y116/EE2BEG2",
"pin": "J15",
- "wire": "VBRK_X29Y129/VBRK_NE2A3"
+ "wire": "VBRK_X9Y121/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV11",
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3",
+ "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0",
+ "HCLK_L_X4Y78/HCLK_LV4",
+ "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LV_L12",
+ "INT_L_X0Y101/LV_L13",
+ "INT_L_X0Y102/LV_L14",
+ "INT_L_X0Y103/LV_L15",
+ "INT_L_X0Y104/LV_L16",
+ "INT_L_X0Y105/LV_L17",
+ "INT_L_X0Y106/LV_L18",
+ "INT_L_X0Y106/NE6A3",
+ "INT_L_X0Y106/NW6BEG3",
+ "INT_L_X0Y107/NE6B3",
+ "INT_L_X0Y108/NE6C3",
+ "INT_L_X0Y109/NE6D3",
+ "INT_L_X0Y110/NE6E3",
+ "INT_L_X0Y116/EE2BEG2",
+ "INT_L_X0Y116/EE2END2",
+ "INT_L_X0Y116/WW2A2",
+ "INT_L_X0Y51/LOGIC_OUTS_L18",
+ "INT_L_X0Y51/NR1BEG0",
+ "INT_L_X0Y52/LV_L0",
+ "INT_L_X0Y52/NR1END0",
+ "INT_L_X0Y53/LV_L1",
+ "INT_L_X0Y54/LV_L2",
+ "INT_L_X0Y55/LV_L3",
+ "INT_L_X0Y56/LV_L4",
+ "INT_L_X0Y57/LV_L5",
+ "INT_L_X0Y58/LV_L6",
+ "INT_L_X0Y59/LV_L7",
+ "INT_L_X0Y60/LV_L8",
+ "INT_L_X0Y61/LV_L9",
+ "INT_L_X0Y62/LV_L10",
+ "INT_L_X0Y63/LV_L11",
+ "INT_L_X0Y64/LV_L12",
+ "INT_L_X0Y65/LV_L13",
+ "INT_L_X0Y66/LV_L14",
+ "INT_L_X0Y67/LV_L15",
+ "INT_L_X0Y68/LV_L16",
+ "INT_L_X0Y69/LV_L17",
+ "INT_L_X0Y70/LV_L0",
+ "INT_L_X0Y70/LV_L18",
+ "INT_L_X0Y71/LV_L1",
+ "INT_L_X0Y72/LV_L2",
+ "INT_L_X0Y73/LV_L3",
+ "INT_L_X0Y74/LV_L4",
+ "INT_L_X0Y75/LV_L5",
+ "INT_L_X0Y76/LV_L6",
+ "INT_L_X0Y77/LV_L7",
+ "INT_L_X0Y78/LV_L8",
+ "INT_L_X0Y79/LV_L9",
+ "INT_L_X0Y80/LV_L10",
+ "INT_L_X0Y81/LV_L11",
+ "INT_L_X0Y82/LV_L12",
+ "INT_L_X0Y83/LV_L13",
+ "INT_L_X0Y84/LV_L14",
+ "INT_L_X0Y85/LV_L15",
+ "INT_L_X0Y86/LV_L16",
+ "INT_L_X0Y87/LV_L17",
+ "INT_L_X0Y88/LV_L0",
+ "INT_L_X0Y88/LV_L18",
+ "INT_L_X0Y89/LV_L1",
+ "INT_L_X0Y90/LV_L2",
+ "INT_L_X0Y91/LV_L3",
+ "INT_L_X0Y92/LV_L4",
+ "INT_L_X0Y93/LV_L5",
+ "INT_L_X0Y94/LV_L6",
+ "INT_L_X0Y95/LV_L7",
+ "INT_L_X0Y96/LV_L8",
+ "INT_L_X0Y97/LV_L9",
+ "INT_L_X0Y98/LV_L10",
+ "INT_L_X0Y99/LV_L11",
+ "INT_R_X1Y110/NE6END3",
+ "INT_R_X1Y110/NN6BEG3",
+ "INT_R_X1Y111/NN6A3",
+ "INT_R_X1Y112/NN6B3",
+ "INT_R_X1Y113/NN6C3",
+ "INT_R_X1Y114/NN6D3",
+ "INT_R_X1Y115/NN6E3",
+ "INT_R_X1Y116/EE2A2",
+ "INT_R_X1Y116/NN6END3",
+ "INT_R_X1Y116/WW2BEG2",
+ "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_NE4BEG3",
+ "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_NW4A3",
+ "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_EE2A2",
+ "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_WW2END2",
+ "IO_INT_INTERFACE_L_X0Y51/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y51/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y51/IOB_IBUF1",
+ "LIOI3_X0Y51/IOI_ILOGIC1_O",
+ "LIOI3_X0Y51/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y51/LIOI_I1",
+ "LIOI3_X0Y51/LIOI_IBUF1",
+ "LIOI3_X0Y51/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y111/L_TERM_INT_NW4BEG3",
+ "L_TERM_INT_X2Y121/L_TERM_INT_WW2A2",
+ "L_TERM_INT_X2Y54/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y121/VBRK_EE2A2"
+ ]
},
{
"name": "dout[0]",
- "node": "INT_L_X10Y125/SW6BEG0",
+ "node": "INT_L_X2Y133/SW6BEG0",
"pin": "U12",
- "wire": "VBRK_X29Y131/VBRK_SW4A0"
+ "wire": "VBRK_X9Y139/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8",
+ "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_8",
+ "INT_INTERFACE_R_X1Y133/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y129/SW6END0",
+ "INT_R_X1Y129/SW6E0",
+ "INT_R_X1Y130/SW6D0",
+ "INT_R_X1Y131/SW6C0",
+ "INT_R_X1Y132/SW6B0",
+ "INT_R_X1Y133/SW6A0",
+ "VBRK_X9Y139/VBRK_SW4A0"
+ ]
},
{
"name": "dout[1]",
- "node": "INT_L_X10Y128/SW6BEG0",
+ "node": "INT_L_X2Y135/SW6BEG0",
"pin": "V12",
- "wire": "VBRK_X29Y134/VBRK_SW4A0"
+ "wire": "VBRK_X9Y141/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_10",
+ "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_10",
+ "INT_INTERFACE_R_X1Y135/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y131/SW6END0",
+ "INT_R_X1Y131/SW6E0",
+ "INT_R_X1Y132/SW6D0",
+ "INT_R_X1Y133/SW6C0",
+ "INT_R_X1Y134/SW6B0",
+ "INT_R_X1Y135/SW6A0",
+ "VBRK_X9Y141/VBRK_SW4A0"
+ ]
},
{
"name": "dout[2]",
- "node": "INT_L_X10Y131/SW6BEG0",
+ "node": "INT_L_X2Y137/SW6BEG0",
"pin": "V10",
- "wire": "VBRK_X29Y137/VBRK_SW4A0"
+ "wire": "VBRK_X9Y143/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_0",
+ "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_0",
+ "INT_INTERFACE_R_X1Y137/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y133/SW6END0",
+ "INT_R_X1Y133/SW6E0",
+ "INT_R_X1Y134/SW6D0",
+ "INT_R_X1Y135/SW6C0",
+ "INT_R_X1Y136/SW6B0",
+ "INT_R_X1Y137/SW6A0",
+ "VBRK_X9Y143/VBRK_SW4A0"
+ ]
},
{
"name": "dout[3]",
- "node": "INT_L_X10Y134/SW6BEG0",
+ "node": "INT_L_X2Y139/SW6BEG0",
"pin": "V11",
- "wire": "VBRK_X29Y140/VBRK_SW4A0"
+ "wire": "VBRK_X9Y145/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_2",
+ "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_2",
+ "INT_INTERFACE_R_X1Y139/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y135/SW6END0",
+ "INT_R_X1Y135/SW6E0",
+ "INT_R_X1Y136/SW6D0",
+ "INT_R_X1Y137/SW6C0",
+ "INT_R_X1Y138/SW6B0",
+ "INT_R_X1Y139/SW6A0",
+ "VBRK_X9Y145/VBRK_SW4A0"
+ ]
},
{
"name": "dout[4]",
- "node": "INT_L_X10Y137/SW6BEG0",
+ "node": "INT_L_X2Y141/SW6BEG0",
"pin": "U14",
- "wire": "VBRK_X29Y143/VBRK_SW4A0"
+ "wire": "VBRK_X9Y147/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_4",
+ "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_4",
+ "INT_INTERFACE_R_X1Y141/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y137/SW6END0",
+ "INT_R_X1Y137/SW6E0",
+ "INT_R_X1Y138/SW6D0",
+ "INT_R_X1Y139/SW6C0",
+ "INT_R_X1Y140/SW6B0",
+ "INT_R_X1Y141/SW6A0",
+ "VBRK_X9Y147/VBRK_SW4A0"
+ ]
},
{
"name": "dout[5]",
- "node": "INT_L_X10Y140/SW6BEG0",
+ "node": "INT_L_X2Y143/SW6BEG0",
"pin": "V14",
- "wire": "VBRK_X29Y146/VBRK_SW4A0"
+ "wire": "VBRK_X9Y149/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_6",
+ "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_6",
+ "INT_INTERFACE_R_X1Y143/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y139/SW6END0",
+ "INT_R_X1Y139/SW6E0",
+ "INT_R_X1Y140/SW6D0",
+ "INT_R_X1Y141/SW6C0",
+ "INT_R_X1Y142/SW6B0",
+ "INT_R_X1Y143/SW6A0",
+ "VBRK_X9Y149/VBRK_SW4A0"
+ ]
},
{
"name": "dout[6]",
- "node": "INT_L_X10Y143/SW6BEG0",
+ "node": "INT_L_X2Y145/SW6BEG0",
"pin": "T13",
- "wire": "VBRK_X29Y149/VBRK_SW4A0"
+ "wire": "VBRK_X9Y151/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_8",
+ "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_8",
+ "INT_INTERFACE_R_X1Y145/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y141/SW6END0",
+ "INT_R_X1Y141/SW6E0",
+ "INT_R_X1Y142/SW6D0",
+ "INT_R_X1Y143/SW6C0",
+ "INT_R_X1Y144/SW6B0",
+ "INT_R_X1Y145/SW6A0",
+ "VBRK_X9Y151/VBRK_SW4A0"
+ ]
},
{
"name": "dout[7]",
- "node": "INT_L_X10Y146/SW6BEG0",
+ "node": "INT_L_X2Y147/SW6BEG0",
"pin": "U13",
- "wire": "VBRK_X29Y152/VBRK_SW4A0"
+ "wire": "VBRK_X9Y153/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_10",
+ "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_10",
+ "INT_INTERFACE_R_X1Y147/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y143/SW6END0",
+ "INT_R_X1Y143/SW6E0",
+ "INT_R_X1Y144/SW6D0",
+ "INT_R_X1Y145/SW6C0",
+ "INT_R_X1Y146/SW6B0",
+ "INT_R_X1Y147/SW6A0",
+ "VBRK_X9Y153/VBRK_SW4A0"
+ ]
}
+ ],
+ "required_features": [
+ "",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O",
+ "CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
+ "CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y142.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y38.GCLK0_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
+ "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
+ "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_BELOW",
+ "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
+ "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
+ "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0",
+ "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
+ "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+ "INT_L_X0Y10.IMUX_L34.SS2END1",
+ "INT_L_X0Y10.SL1BEG1.SR1END1",
+ "INT_L_X0Y100.LVB_L0.LV_L18",
+ "INT_L_X0Y101.SE6BEG0.LV_L0",
+ "INT_L_X0Y102.EE2BEG2.NN6END2",
+ "INT_L_X0Y103.LV_L18.LV_L0",
+ "INT_L_X0Y103.NN6BEG2.LVB_L12",
+ "INT_L_X0Y104.EE2BEG2.ER1END2",
+ "INT_L_X0Y104.WR1BEG2.NN6END1",
+ "INT_L_X0Y105.LV_L18.LV_L0",
+ "INT_L_X0Y105.NN2BEG3.NN6END3",
+ "INT_L_X0Y106.EE2BEG2.SS6END2",
+ "INT_L_X0Y106.NW6BEG3.LV_L18",
+ "INT_L_X0Y107.LVB_L12.LV_L0",
+ "INT_L_X0Y107.NL1BEG2.NN2END3",
+ "INT_L_X0Y107.NN6BEG3.LV_L18",
+ "INT_L_X0Y108.EE2BEG2.NL1END2",
+ "INT_L_X0Y108.NW6BEG3.LV_L18",
+ "INT_L_X0Y109.NR1BEG2.NN6END2",
+ "INT_L_X0Y11.SR1BEG1.SS6END0",
+ "INT_L_X0Y11.SS6BEG2.SS6END2",
+ "INT_L_X0Y110.EE2BEG2.NR1END2",
+ "INT_L_X0Y111.LV_L18.LV_L0",
+ "INT_L_X0Y112.EE2BEG2.EL1END2",
+ "INT_L_X0Y112.SS6BEG2.LVB_L12",
+ "INT_L_X0Y112.WL1BEG2.WR1END_S1_0",
+ "INT_L_X0Y113.LV_L18.LV_L0",
+ "INT_L_X0Y113.NL1BEG2.NN6END3",
+ "INT_L_X0Y114.EE2BEG2.NL1END2",
+ "INT_L_X0Y115.LV_L18.LV_L0",
+ "INT_L_X0Y116.EE2BEG2.EE2END2",
+ "INT_L_X0Y117.LV_L18.LV_L0",
+ "INT_L_X0Y119.LV_L18.LV_L0",
+ "INT_L_X0Y12.SS2BEG1.SR1END1",
+ "INT_L_X0Y121.LV_L18.LV_L0",
+ "INT_L_X0Y123.LV_L18.LV_L0",
+ "INT_L_X0Y125.LV_L18.LV_L0",
+ "INT_L_X0Y129.LV_L18.SW6END0",
+ "INT_L_X0Y13.SE6BEG0.SS6END0",
+ "INT_L_X0Y13.SR1BEG1.SS2END0",
+ "INT_L_X0Y13.SS6BEG0.LV_L0",
+ "INT_L_X0Y131.LV_L18.SW6END0",
+ "INT_L_X0Y133.LV_L18.SW6END0",
+ "INT_L_X0Y135.LV_L18.SW6END0",
+ "INT_L_X0Y137.LV_L18.SW6END0",
+ "INT_L_X0Y139.LV_L18.SW6END0",
+ "INT_L_X0Y141.LV_L18.SW6END0",
+ "INT_L_X0Y143.LV_L18.SW6END0",
+ "INT_L_X0Y15.SS2BEG0.SS6END0",
+ "INT_L_X0Y15.SS6BEG0.LV_L0",
+ "INT_L_X0Y15.SS6BEG2.SS6END2",
+ "INT_L_X0Y17.SS6BEG0.SS6END0",
+ "INT_L_X0Y17.SS6BEG2.SS6END2",
+ "INT_L_X0Y19.SS6BEG0.SS6END0",
+ "INT_L_X0Y21.SS6BEG0.LV_L0",
+ "INT_L_X0Y21.SS6BEG2.SS6END2",
+ "INT_L_X0Y23.SS6BEG0.LV_L0",
+ "INT_L_X0Y23.SS6BEG2.SS6END2",
+ "INT_L_X0Y25.SS6BEG0.LV_L0",
+ "INT_L_X0Y27.SS6BEG2.SS6END2",
+ "INT_L_X0Y29.SS6BEG2.SS6END2",
+ "INT_L_X0Y3.FAN_ALT1.SS2END2",
+ "INT_L_X0Y3.IMUX_L34.FAN_BOUNCE1",
+ "INT_L_X0Y31.LV_L18.LV_L0",
+ "INT_L_X0Y33.LV_L18.LV_L0",
+ "INT_L_X0Y33.SS6BEG2.SS6END2",
+ "INT_L_X0Y35.SS6BEG2.SS6END2",
+ "INT_L_X0Y39.LV_L18.LV_L0",
+ "INT_L_X0Y39.SS6BEG2.SS6END2",
+ "INT_L_X0Y4.IMUX_L34.SS2END1",
+ "INT_L_X0Y41.LV_L18.LV_L0",
+ "INT_L_X0Y41.SS6BEG2.SS6END2",
+ "INT_L_X0Y43.LV_L18.LV_L0",
+ "INT_L_X0Y45.SS6BEG2.SS6END2",
+ "INT_L_X0Y47.SS6BEG2.SS6END2",
+ "INT_L_X0Y49.LV_L18.LV_L0",
+ "INT_L_X0Y5.BYP_ALT0.SS2END0",
+ "INT_L_X0Y5.IMUX_L34.BYP_BOUNCE0",
+ "INT_L_X0Y5.SS2BEG2.SS6END2",
+ "INT_L_X0Y51.LV_L18.LV_L0",
+ "INT_L_X0Y51.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y51.SS6BEG2.SS6END2",
+ "INT_L_X0Y52.LV_L0.NR1END0",
+ "INT_L_X0Y52.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y53.LV_L0.NR1END0",
+ "INT_L_X0Y53.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y53.SS6BEG2.SS6END2",
+ "INT_L_X0Y54.LV_L0.NR1END0",
+ "INT_L_X0Y54.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y55.LV_L0.NR1END0",
+ "INT_L_X0Y57.LV_L18.LV_L0",
+ "INT_L_X0Y57.SS6BEG2.SS6END2",
+ "INT_L_X0Y59.LV_L18.LV_L0",
+ "INT_L_X0Y59.SS6BEG2.LVB_L0",
+ "INT_L_X0Y6.FAN_ALT1.EL1END3",
+ "INT_L_X0Y6.IMUX_L34.FAN_BOUNCE1",
+ "INT_L_X0Y6.SS2BEG1.SR1END1",
+ "INT_L_X0Y61.LV_L18.LV_L0",
+ "INT_L_X0Y63.SS6BEG2.LVB_L0",
+ "INT_L_X0Y67.LV_L18.LV_L0",
+ "INT_L_X0Y69.LV_L18.LV_L0",
+ "INT_L_X0Y7.FAN_ALT1.SS2END2",
+ "INT_L_X0Y7.IMUX_L34.FAN_BOUNCE1",
+ "INT_L_X0Y7.SR1BEG1.SS2END0",
+ "INT_L_X0Y7.SS2BEG0.SS6END0",
+ "INT_L_X0Y7.WL1BEG_N3.SW6END0",
+ "INT_L_X0Y70.LV_L0.LV_L18",
+ "INT_L_X0Y71.LVB_L12.LVB_L0",
+ "INT_L_X0Y71.LV_L0.LV_L18",
+ "INT_L_X0Y72.LV_L0.LV_L18",
+ "INT_L_X0Y73.LV_L0.LV_L18",
+ "INT_L_X0Y75.LVB_L12.LVB_L0",
+ "INT_L_X0Y75.LV_L18.LV_L0",
+ "INT_L_X0Y75.NN6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y76.NN6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y77.LV_L18.LV_L0",
+ "INT_L_X0Y77.NN6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y78.NN6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y79.LV_L18.LV_L0",
+ "INT_L_X0Y8.IMUX_L34.WW2END0",
+ "INT_L_X0Y81.LV_L0.NN6END0",
+ "INT_L_X0Y82.LV_L0.NN6END0",
+ "INT_L_X0Y83.LVB_L12.LVB_L0",
+ "INT_L_X0Y83.LV_L0.NN6END0",
+ "INT_L_X0Y84.LVB_L0.LV_L0",
+ "INT_L_X0Y84.LV_L0.NN6END0",
+ "INT_L_X0Y85.LV_L18.LV_L0",
+ "INT_L_X0Y87.LVB_L12.LVB_L0",
+ "INT_L_X0Y87.LV_L18.LV_L0",
+ "INT_L_X0Y88.LV_L0.LV_L18",
+ "INT_L_X0Y89.LV_L0.LV_L18",
+ "INT_L_X0Y9.IMUX_L34.SL1END1",
+ "INT_L_X0Y9.SS2BEG0.SS6END0",
+ "INT_L_X0Y9.SS2BEG2.SS6END2",
+ "INT_L_X0Y90.LV_L0.LV_L18",
+ "INT_L_X0Y91.LVB_L0.LV_L18",
+ "INT_L_X0Y92.NN6BEG1.LV_L9",
+ "INT_L_X0Y93.LV_L18.LV_L0",
+ "INT_L_X0Y95.LVB_L12.LVB_L0",
+ "INT_L_X0Y95.LV_L18.LV_L0",
+ "INT_L_X0Y96.NN6BEG2.LVB_L12",
+ "INT_L_X0Y97.LV_L18.LV_L0",
+ "INT_L_X0Y98.NN6BEG1.NN6END1",
+ "INT_L_X0Y99.LVB_L12.LV_L0",
+ "INT_L_X0Y99.NN6BEG3.LV_L18",
+ "INT_L_X0Y99.SE6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X10Y79.EE2BEG0.SE6END0",
+ "INT_L_X18Y79.SE6BEG0.EE2END0",
+ "INT_L_X20Y75.SE6BEG0.SE6END0",
+ "INT_L_X22Y47.SE2BEG0.SS6END0",
+ "INT_L_X22Y53.SS6BEG0.SS6END0",
+ "INT_L_X22Y59.SS6BEG0.SS6END0",
+ "INT_L_X22Y65.SS6BEG0.SS6END0",
+ "INT_L_X22Y71.SS6BEG0.SE6END0",
+ "INT_L_X2Y11.SW6BEG0.SS6END0",
+ "INT_L_X2Y17.SS6BEG0.LV_L0",
+ "INT_L_X2Y35.LV_L18.LV_L0",
+ "INT_L_X2Y53.LV_L18.LV_L0",
+ "INT_L_X2Y71.LV_L18.LV_L0",
+ "INT_L_X2Y8.WW2BEG0.SL1END0",
+ "INT_L_X2Y89.LV_L18.SW6END0",
+ "INT_L_X2Y9.SL1BEG0.SE6END0",
+ "INT_L_X2Y95.SE6BEG0.SE6END0",
+ "INT_L_X2Y97.SE6BEG0.SE6END0",
+ "INT_L_X4Y91.SE6BEG0.SE6END0",
+ "INT_L_X4Y93.SW6BEG0.SE6END0",
+ "INT_L_X6Y87.SE6BEG0.SE6END0",
+ "INT_L_X8Y83.SE6BEG0.SE6END0",
+ "INT_R_X1Y110.NN6BEG3.NE6END3",
+ "INT_R_X1Y112.WR1BEG_S0.NE6END3",
+ "INT_R_X1Y116.WW2BEG2.NN6END3",
+ "INT_R_X23Y46.IMUX24.SE2END0",
+ "LIOB33_SING_X0Y99.IOB_Y1.IN_ONLY",
+ "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_SING_X0Y99.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_SING_X0Y99.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_SING_X0Y99.IOB_Y1.SLEW.FAST",
+ "LIOB33_SING_X0Y99.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y3.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y3.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y3.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y3.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y3.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y3.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y3.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y3.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
+ "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y5.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y5.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y5.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y5.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y5.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y5.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y5.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y5.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y51.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y51.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y51.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y51.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y51.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y51.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y51.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y51.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y51.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y51.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y51.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y51.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y53.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y53.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y53.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y53.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y53.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y53.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y53.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y53.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y53.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y53.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y53.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y53.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y7.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y7.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y7.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y7.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y7.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y7.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y7.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y7.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y75.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y75.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y75.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y75.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y75.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y75.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y75.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y75.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y77.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y77.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y77.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y77.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y77.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y77.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y77.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y77.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y77.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y77.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y77.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y77.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y9.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y9.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y9.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y9.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y9.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y9.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y9.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y9.IOB_Y1.SLEW.SLOW"
]
-}
\ No newline at end of file
+}
diff --git a/artix7/harness/arty-a7/pmod/design.txt b/artix7/harness/arty-a7/pmod/design.txt
index 09a8861..7b7ecc8 100644
--- a/artix7/harness/arty-a7/pmod/design.txt
+++ b/artix7/harness/arty-a7/pmod/design.txt
@@ -1,18 +1,18 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 G13 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
-din[0] INT_R_X9Y102/NE2BEG3 E15 VBRK_X29Y108/VBRK_NE2A3
-din[1] INT_R_X9Y105/NE2BEG3 E16 VBRK_X29Y111/VBRK_NE2A3
-din[2] INT_R_X9Y108/NE2BEG3 D15 VBRK_X29Y114/VBRK_NE2A3
-din[3] INT_R_X9Y111/NE2BEG3 C15 VBRK_X29Y117/VBRK_NE2A3
-din[4] INT_R_X9Y114/NE2BEG3 J17 VBRK_X29Y120/VBRK_NE2A3
-din[5] INT_R_X9Y117/NE2BEG3 J18 VBRK_X29Y123/VBRK_NE2A3
-din[6] INT_R_X9Y120/NE2BEG3 K15 VBRK_X29Y126/VBRK_NE2A3
-din[7] INT_R_X9Y123/NE2BEG3 J15 VBRK_X29Y129/VBRK_NE2A3
-dout[0] INT_L_X10Y125/SW6BEG0 U12 VBRK_X29Y131/VBRK_SW4A0
-dout[1] INT_L_X10Y128/SW6BEG0 V12 VBRK_X29Y134/VBRK_SW4A0
-dout[2] INT_L_X10Y131/SW6BEG0 V10 VBRK_X29Y137/VBRK_SW4A0
-dout[3] INT_L_X10Y134/SW6BEG0 V11 VBRK_X29Y140/VBRK_SW4A0
-dout[4] INT_L_X10Y137/SW6BEG0 U14 VBRK_X29Y143/VBRK_SW4A0
-dout[5] INT_L_X10Y140/SW6BEG0 V14 VBRK_X29Y146/VBRK_SW4A0
-dout[6] INT_L_X10Y143/SW6BEG0 T13 VBRK_X29Y149/VBRK_SW4A0
-dout[7] INT_L_X10Y146/SW6BEG0 U13 VBRK_X29Y152/VBRK_SW4A0
+din[0] INT_L_X0Y102/EE2BEG2 E15 VBRK_X9Y107/VBRK_EE2A2
+din[1] INT_L_X0Y104/EE2BEG2 E16 VBRK_X9Y109/VBRK_EE2A2
+din[2] INT_L_X0Y106/EE2BEG2 D15 VBRK_X9Y111/VBRK_EE2A2
+din[3] INT_L_X0Y108/EE2BEG2 C15 VBRK_X9Y113/VBRK_EE2A2
+din[4] INT_L_X0Y110/EE2BEG2 J17 VBRK_X9Y115/VBRK_EE2A2
+din[5] INT_L_X0Y112/EE2BEG2 J18 VBRK_X9Y117/VBRK_EE2A2
+din[6] INT_L_X0Y114/EE2BEG2 K15 VBRK_X9Y119/VBRK_EE2A2
+din[7] INT_L_X0Y116/EE2BEG2 J15 VBRK_X9Y121/VBRK_EE2A2
+dout[0] INT_L_X2Y133/SW6BEG0 U12 VBRK_X9Y139/VBRK_SW4A0
+dout[1] INT_L_X2Y135/SW6BEG0 V12 VBRK_X9Y141/VBRK_SW4A0
+dout[2] INT_L_X2Y137/SW6BEG0 V10 VBRK_X9Y143/VBRK_SW4A0
+dout[3] INT_L_X2Y139/SW6BEG0 V11 VBRK_X9Y145/VBRK_SW4A0
+dout[4] INT_L_X2Y141/SW6BEG0 U14 VBRK_X9Y147/VBRK_SW4A0
+dout[5] INT_L_X2Y143/SW6BEG0 V14 VBRK_X9Y149/VBRK_SW4A0
+dout[6] INT_L_X2Y145/SW6BEG0 T13 VBRK_X9Y151/VBRK_SW4A0
+dout[7] INT_L_X2Y147/SW6BEG0 U13 VBRK_X9Y153/VBRK_SW4A0
diff --git a/artix7/harness/arty-a7/swbut/design.bit b/artix7/harness/arty-a7/swbut/design.bit
index e37d015..220c617 100644
--- a/artix7/harness/arty-a7/swbut/design.bit
+++ b/artix7/harness/arty-a7/swbut/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.dcp b/artix7/harness/arty-a7/swbut/design.dcp
index b02810f..2180649 100644
--- a/artix7/harness/arty-a7/swbut/design.dcp
+++ b/artix7/harness/arty-a7/swbut/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.json b/artix7/harness/arty-a7/swbut/design.json
index f01eb9e..23f4932 100644
--- a/artix7/harness/arty-a7/swbut/design.json
+++ b/artix7/harness/arty-a7/swbut/design.json
@@ -1,8 +1,8 @@
{
"info": {
- "GRID_X_MAX": 47,
- "GRID_X_MIN": 18,
- "GRID_Y_MAX": 52,
+ "GRID_X_MAX": 58,
+ "GRID_X_MIN": 10,
+ "GRID_Y_MAX": 51,
"GRID_Y_MIN": 0
},
"ports": [
@@ -14,99 +14,1057 @@
},
{
"name": "din[0]",
- "node": "INT_R_X9Y102/NE2BEG3",
+ "node": "INT_L_X0Y102/EE2BEG2",
"pin": "A8",
- "wire": "VBRK_X29Y108/VBRK_NE2A3"
+ "wire": "VBRK_X9Y107/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_LVB_L4",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2",
+ "HCLK_L_X4Y130/HCLK_LV16",
+ "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LVB_L4",
+ "INT_L_X0Y101/LVB_L5",
+ "INT_L_X0Y102/EE2BEG2",
+ "INT_L_X0Y102/LVB_L6",
+ "INT_L_X0Y102/SS6END2",
+ "INT_L_X0Y103/LVB_L7",
+ "INT_L_X0Y103/SS6E2",
+ "INT_L_X0Y104/LVB_L8",
+ "INT_L_X0Y104/SS6D2",
+ "INT_L_X0Y105/LVB_L9",
+ "INT_L_X0Y105/SS6C2",
+ "INT_L_X0Y106/LVB_L10",
+ "INT_L_X0Y106/SS6B2",
+ "INT_L_X0Y107/LVB_L11",
+ "INT_L_X0Y107/SS6A2",
+ "INT_L_X0Y108/LVB_L12",
+ "INT_L_X0Y108/LV_L0",
+ "INT_L_X0Y108/SS6BEG2",
+ "INT_L_X0Y109/LV_L1",
+ "INT_L_X0Y110/LV_L2",
+ "INT_L_X0Y111/LV_L3",
+ "INT_L_X0Y112/LV_L4",
+ "INT_L_X0Y113/LV_L5",
+ "INT_L_X0Y114/LV_L6",
+ "INT_L_X0Y115/LV_L7",
+ "INT_L_X0Y116/LV_L8",
+ "INT_L_X0Y117/LV_L9",
+ "INT_L_X0Y118/LV_L10",
+ "INT_L_X0Y119/LV_L11",
+ "INT_L_X0Y120/LV_L12",
+ "INT_L_X0Y121/LV_L13",
+ "INT_L_X0Y122/LV_L14",
+ "INT_L_X0Y123/LV_L15",
+ "INT_L_X0Y124/LV_L16",
+ "INT_L_X0Y125/LOGIC_OUTS_L18",
+ "INT_L_X0Y125/LV_L17",
+ "INT_L_X0Y125/NR1BEG0",
+ "INT_L_X0Y126/LV_L18",
+ "INT_L_X0Y126/NR1END0",
+ "INT_L_X0Y96/LVB_L0",
+ "INT_L_X0Y97/LVB_L1",
+ "INT_L_X0Y98/LVB_L2",
+ "INT_L_X0Y99/LVB_L3",
+ "INT_R_X1Y102/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y125/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y125/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y125/IOB_IBUF1",
+ "LIOI3_X0Y125/IOI_ILOGIC1_O",
+ "LIOI3_X0Y125/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y125/LIOI_I1",
+ "LIOI3_X0Y125/LIOI_IBUF1",
+ "LIOI3_X0Y125/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y131/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y107/VBRK_EE2A2"
+ ]
},
{
"name": "din[1]",
- "node": "INT_R_X9Y105/NE2BEG3",
+ "node": "INT_L_X0Y104/EE2BEG2",
"pin": "C11",
- "wire": "VBRK_X29Y111/VBRK_NE2A3"
+ "wire": "VBRK_X9Y109/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "BRKH_INT_X0Y99/BRKH_INT_L_LV10",
+ "BRKH_INT_X0Y99/BRKH_INT_NN6A1",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4",
+ "HCLK_L_X4Y130/HCLK_LV17",
+ "HCLK_L_X4Y130/HCLK_NR1BEG0",
+ "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y100/LV_L11",
+ "INT_L_X0Y100/NN6B1",
+ "INT_L_X0Y101/LV_L12",
+ "INT_L_X0Y101/NN6C1",
+ "INT_L_X0Y102/LV_L13",
+ "INT_L_X0Y102/NN6D1",
+ "INT_L_X0Y103/LV_L14",
+ "INT_L_X0Y103/NN6E1",
+ "INT_L_X0Y104/EE2BEG2",
+ "INT_L_X0Y104/ER1END2",
+ "INT_L_X0Y104/LV_L15",
+ "INT_L_X0Y104/NN6END1",
+ "INT_L_X0Y104/WR1BEG2",
+ "INT_L_X0Y105/LV_L16",
+ "INT_L_X0Y106/LV_L17",
+ "INT_L_X0Y107/LV_L0",
+ "INT_L_X0Y107/LV_L18",
+ "INT_L_X0Y108/LV_L1",
+ "INT_L_X0Y109/LV_L2",
+ "INT_L_X0Y110/LV_L3",
+ "INT_L_X0Y111/LV_L4",
+ "INT_L_X0Y112/LV_L5",
+ "INT_L_X0Y113/LV_L6",
+ "INT_L_X0Y114/LV_L7",
+ "INT_L_X0Y115/LV_L8",
+ "INT_L_X0Y116/LV_L9",
+ "INT_L_X0Y117/LV_L10",
+ "INT_L_X0Y118/LV_L11",
+ "INT_L_X0Y119/LV_L12",
+ "INT_L_X0Y120/LV_L13",
+ "INT_L_X0Y121/LV_L14",
+ "INT_L_X0Y122/LV_L15",
+ "INT_L_X0Y123/LV_L16",
+ "INT_L_X0Y124/LOGIC_OUTS_L18",
+ "INT_L_X0Y124/LV_L17",
+ "INT_L_X0Y124/NR1BEG0",
+ "INT_L_X0Y125/LV_L18",
+ "INT_L_X0Y125/NR1END0",
+ "INT_L_X0Y89/LV_L0",
+ "INT_L_X0Y90/LV_L1",
+ "INT_L_X0Y91/LV_L2",
+ "INT_L_X0Y92/LV_L3",
+ "INT_L_X0Y93/LV_L4",
+ "INT_L_X0Y94/LV_L5",
+ "INT_L_X0Y95/LV_L6",
+ "INT_L_X0Y96/LV_L7",
+ "INT_L_X0Y97/LV_L8",
+ "INT_L_X0Y98/LV_L9",
+ "INT_L_X0Y98/NN6BEG1",
+ "INT_L_X0Y99/LV_L10",
+ "INT_L_X0Y99/NN6A1",
+ "INT_R_X1Y104/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_ER1BEG2",
+ "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_WR1END2",
+ "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y123/IOB_IBUF0",
+ "LIOI3_X0Y123/IOI_ILOGIC0_O",
+ "LIOI3_X0Y123/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y123/LIOI_I0",
+ "LIOI3_X0Y123/LIOI_IBUF0",
+ "LIOI3_X0Y123/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y109/L_TERM_INT_WR1BEG3",
+ "L_TERM_INT_X2Y129/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y109/VBRK_EE2A2"
+ ]
},
{
"name": "din[2]",
- "node": "INT_R_X9Y108/NE2BEG3",
+ "node": "INT_L_X0Y106/EE2BEG2",
"pin": "C10",
- "wire": "VBRK_X29Y114/VBRK_NE2A3"
+ "wire": "VBRK_X9Y111/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6",
+ "INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y106/EE2BEG2",
+ "INT_L_X0Y106/SS6END2",
+ "INT_L_X0Y107/SS6E2",
+ "INT_L_X0Y108/SS6D2",
+ "INT_L_X0Y109/SS6C2",
+ "INT_L_X0Y110/SS6B2",
+ "INT_L_X0Y111/SS6A2",
+ "INT_L_X0Y112/LVB_L0",
+ "INT_L_X0Y112/SS6BEG2",
+ "INT_L_X0Y113/LVB_L1",
+ "INT_L_X0Y114/LVB_L2",
+ "INT_L_X0Y115/LVB_L3",
+ "INT_L_X0Y116/LVB_L4",
+ "INT_L_X0Y117/LVB_L5",
+ "INT_L_X0Y118/LVB_L6",
+ "INT_L_X0Y119/LVB_L7",
+ "INT_L_X0Y120/LVB_L8",
+ "INT_L_X0Y121/LVB_L9",
+ "INT_L_X0Y122/LVB_L10",
+ "INT_L_X0Y123/LOGIC_OUTS_L18",
+ "INT_L_X0Y123/LVB_L11",
+ "INT_L_X0Y123/NL1BEG_N3",
+ "INT_L_X0Y123/NR1BEG3",
+ "INT_L_X0Y124/LVB_L12",
+ "INT_L_X0Y124/NR1END3",
+ "INT_R_X1Y106/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y123/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y123/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y123/IOB_IBUF1",
+ "LIOI3_X0Y123/IOI_ILOGIC1_O",
+ "LIOI3_X0Y123/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y123/LIOI_I1",
+ "LIOI3_X0Y123/LIOI_IBUF1",
+ "LIOI3_X0Y123/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y128/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y111/VBRK_EE2A2"
+ ]
},
{
"name": "din[3]",
- "node": "INT_R_X9Y111/NE2BEG3",
+ "node": "INT_L_X0Y108/EE2BEG2",
"pin": "A10",
- "wire": "VBRK_X29Y117/VBRK_NE2A3"
+ "wire": "VBRK_X9Y113/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8",
+ "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y108/EE2BEG2",
+ "INT_L_X0Y108/EL1END2",
+ "INT_L_X0Y108/SL1END3",
+ "INT_L_X0Y108/WL1BEG2",
+ "INT_L_X0Y109/EL1END3",
+ "INT_L_X0Y109/SL1BEG3",
+ "INT_L_X0Y109/WL1BEG3",
+ "INT_L_X0Y110/SS6END0",
+ "INT_L_X0Y110/WL1BEG_N3",
+ "INT_L_X0Y111/SS6E0",
+ "INT_L_X0Y112/SS6D0",
+ "INT_L_X0Y113/SS6C0",
+ "INT_L_X0Y114/SS6B0",
+ "INT_L_X0Y115/SS6A0",
+ "INT_L_X0Y116/SS6BEG0",
+ "INT_L_X0Y116/SS6END0",
+ "INT_L_X0Y117/SS6E0",
+ "INT_L_X0Y118/SS6D0",
+ "INT_L_X0Y119/SS6C0",
+ "INT_L_X0Y120/SS6B0",
+ "INT_L_X0Y121/SS6A0",
+ "INT_L_X0Y122/LOGIC_OUTS_L18",
+ "INT_L_X0Y122/SS6BEG0",
+ "INT_R_X1Y108/EE2A2",
+ "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_EL1BEG2",
+ "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_WL1END2",
+ "IO_INT_INTERFACE_L_X0Y109/INT_INTERFACE_EL1BEG3",
+ "IO_INT_INTERFACE_L_X0Y109/INT_INTERFACE_WL1END3",
+ "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y121/IOB_IBUF0",
+ "LIOI3_X0Y121/IOI_ILOGIC0_O",
+ "LIOI3_X0Y121/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y121/LIOI_I0",
+ "LIOI3_X0Y121/LIOI_IBUF0",
+ "LIOI3_X0Y121/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y113/L_TERM_INT_WL1BEG2",
+ "L_TERM_INT_X2Y114/L_TERM_INT_WR1BEG2",
+ "L_TERM_INT_X2Y127/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y113/VBRK_EE2A2"
+ ]
},
{
"name": "din[4]",
- "node": "INT_R_X9Y114/NE2BEG3",
+ "node": "INT_L_X0Y110/EE2BEG2",
"pin": "D9",
- "wire": "VBRK_X29Y120/VBRK_NE2A3"
+ "wire": "VBRK_X9Y115/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9",
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_WW2A0_9",
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_SE4C0_3",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_WW2A0_10",
+ "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SE4C0_0",
+ "HCLK_L_X4Y130/HCLK_LV4",
+ "INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2",
+ "INT_INTERFACE_R_X1Y110/INT_INTERFACE_WW2A0",
+ "INT_INTERFACE_R_X1Y116/INT_INTERFACE_SE4C0",
+ "INT_L_X0Y110/EE2BEG2",
+ "INT_L_X0Y110/ER1END2",
+ "INT_L_X0Y110/WR1BEG2",
+ "INT_L_X0Y110/WW2END0",
+ "INT_L_X0Y120/LV_L0",
+ "INT_L_X0Y120/SE6BEG0",
+ "INT_L_X0Y121/LV_L1",
+ "INT_L_X0Y122/LV_L2",
+ "INT_L_X0Y123/LV_L3",
+ "INT_L_X0Y124/LV_L4",
+ "INT_L_X0Y125/LV_L5",
+ "INT_L_X0Y126/LV_L6",
+ "INT_L_X0Y127/LV_L7",
+ "INT_L_X0Y128/LV_L8",
+ "INT_L_X0Y129/LV_L9",
+ "INT_L_X0Y130/LV_L10",
+ "INT_L_X0Y131/LV_L11",
+ "INT_L_X0Y132/LV_L12",
+ "INT_L_X0Y133/LV_L13",
+ "INT_L_X0Y134/LV_L14",
+ "INT_L_X0Y135/LV_L15",
+ "INT_L_X0Y136/LV_L16",
+ "INT_L_X0Y137/LOGIC_OUTS_L18",
+ "INT_L_X0Y137/LV_L17",
+ "INT_L_X0Y137/NR1BEG0",
+ "INT_L_X0Y138/LV_L18",
+ "INT_L_X0Y138/NR1END0",
+ "INT_R_X1Y110/EE2A2",
+ "INT_R_X1Y110/WW2A0",
+ "INT_R_X1Y116/SE6E0",
+ "INT_R_X1Y117/SE6D0",
+ "INT_R_X1Y118/SE6C0",
+ "INT_R_X1Y119/SE6B0",
+ "INT_R_X1Y120/SE6A0",
+ "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_ER1BEG2",
+ "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_WR1END2",
+ "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y137/IOB_IBUF1",
+ "LIOI3_TBYTETERM_X0Y137/IOI_ILOGIC1_O",
+ "LIOI3_TBYTETERM_X0Y137/IOI_LOGIC_OUTS18_0",
+ "LIOI3_TBYTETERM_X0Y137/LIOI_I1",
+ "LIOI3_TBYTETERM_X0Y137/LIOI_IBUF1",
+ "LIOI3_TBYTETERM_X0Y137/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y115/L_TERM_INT_WR1BEG3",
+ "L_TERM_INT_X2Y143/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y115/VBRK_EE2A2",
+ "VBRK_X9Y115/VBRK_WW2A0",
+ "VBRK_X9Y121/VBRK_SE4C0"
+ ]
},
{
"name": "din[5]",
- "node": "INT_R_X9Y117/NE2BEG3",
+ "node": "INT_L_X0Y112/EE2BEG2",
"pin": "C9",
- "wire": "VBRK_X29Y123/VBRK_NE2A3"
+ "wire": "VBRK_X9Y117/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12",
+ "HCLK_R_X5Y130/HCLK_LVB9",
+ "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y112/EE2BEG2",
+ "INT_L_X0Y112/SE6END2",
+ "INT_L_X0Y112/SW6E2",
+ "INT_L_X0Y113/SW6D2",
+ "INT_L_X0Y114/SW6C2",
+ "INT_L_X0Y115/SW6B2",
+ "INT_L_X0Y116/SW6A2",
+ "INT_L_X0Y127/EL1BEG3",
+ "INT_L_X0Y128/EL1BEG_N3",
+ "INT_L_X0Y128/LOGIC_OUTS_L18",
+ "INT_R_X1Y112/EE2A2",
+ "INT_R_X1Y116/LVB0",
+ "INT_R_X1Y116/SW6BEG2",
+ "INT_R_X1Y117/LVB1",
+ "INT_R_X1Y118/LVB2",
+ "INT_R_X1Y119/LVB3",
+ "INT_R_X1Y120/LVB4",
+ "INT_R_X1Y121/LVB5",
+ "INT_R_X1Y122/LVB6",
+ "INT_R_X1Y123/LVB7",
+ "INT_R_X1Y124/LVB8",
+ "INT_R_X1Y125/LVB9",
+ "INT_R_X1Y126/LVB10",
+ "INT_R_X1Y127/EL1END3",
+ "INT_R_X1Y127/LVB11",
+ "INT_R_X1Y127/NR1BEG3",
+ "INT_R_X1Y128/LVB12",
+ "INT_R_X1Y128/NR1END3",
+ "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_SE4C2",
+ "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_SW4END2",
+ "IO_INT_INTERFACE_L_X0Y128/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y128/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y127/IOB_IBUF0",
+ "LIOI3_X0Y127/IOI_ILOGIC0_O",
+ "LIOI3_X0Y127/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y127/LIOI_I0",
+ "LIOI3_X0Y127/LIOI_IBUF0",
+ "LIOI3_X0Y127/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y117/L_TERM_INT_SW4C2",
+ "L_TERM_INT_X2Y134/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y117/VBRK_EE2A2"
+ ]
},
{
"name": "din[6]",
- "node": "INT_R_X9Y120/NE2BEG3",
+ "node": "INT_L_X0Y114/EE2BEG2",
"pin": "B9",
- "wire": "VBRK_X29Y126/VBRK_NE2A3"
+ "wire": "VBRK_X9Y119/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1",
+ "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14",
+ "HCLK_L_X4Y130/HCLK_LV14",
+ "INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2",
+ "INT_L_X0Y110/LV_L0",
+ "INT_L_X0Y110/NE6A0",
+ "INT_L_X0Y110/NW6BEG0",
+ "INT_L_X0Y111/LV_L1",
+ "INT_L_X0Y111/NE6B0",
+ "INT_L_X0Y112/LV_L2",
+ "INT_L_X0Y112/NE6C0",
+ "INT_L_X0Y113/LV_L3",
+ "INT_L_X0Y113/NE6D0",
+ "INT_L_X0Y114/EE2BEG2",
+ "INT_L_X0Y114/EL1END2",
+ "INT_L_X0Y114/LV_L4",
+ "INT_L_X0Y114/NE6E0",
+ "INT_L_X0Y114/NW2END_S0_0",
+ "INT_L_X0Y114/WL1BEG2",
+ "INT_L_X0Y115/LV_L5",
+ "INT_L_X0Y115/NW2END0",
+ "INT_L_X0Y116/LV_L6",
+ "INT_L_X0Y117/LV_L7",
+ "INT_L_X0Y118/LV_L8",
+ "INT_L_X0Y119/LV_L9",
+ "INT_L_X0Y120/LV_L10",
+ "INT_L_X0Y121/LV_L11",
+ "INT_L_X0Y122/LV_L12",
+ "INT_L_X0Y123/LV_L13",
+ "INT_L_X0Y124/LV_L14",
+ "INT_L_X0Y125/LV_L15",
+ "INT_L_X0Y126/LV_L16",
+ "INT_L_X0Y127/LOGIC_OUTS_L18",
+ "INT_L_X0Y127/LV_L17",
+ "INT_L_X0Y127/NR1BEG0",
+ "INT_L_X0Y128/LV_L18",
+ "INT_L_X0Y128/NR1END0",
+ "INT_R_X1Y114/EE2A2",
+ "INT_R_X1Y114/NE6END0",
+ "INT_R_X1Y114/NW2BEG0",
+ "INT_R_X1Y115/NW2A0",
+ "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_NE4BEG0",
+ "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_NW4A0",
+ "IO_INT_INTERFACE_L_X0Y114/INT_INTERFACE_EL1BEG2",
+ "IO_INT_INTERFACE_L_X0Y114/INT_INTERFACE_WL1END2",
+ "IO_INT_INTERFACE_L_X0Y127/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y127/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y127/IOB_IBUF1",
+ "LIOI3_X0Y127/IOI_ILOGIC1_O",
+ "LIOI3_X0Y127/IOI_LOGIC_OUTS18_0",
+ "LIOI3_X0Y127/LIOI_I1",
+ "LIOI3_X0Y127/LIOI_IBUF1",
+ "LIOI3_X0Y127/LIOI_ILOGIC1_D",
+ "L_TERM_INT_X2Y115/L_TERM_INT_NW4BEG0",
+ "L_TERM_INT_X2Y119/L_TERM_INT_WL1BEG2",
+ "L_TERM_INT_X2Y133/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y119/VBRK_EE2A2"
+ ]
},
{
"name": "din[7]",
- "node": "INT_R_X9Y123/NE2BEG3",
+ "node": "INT_L_X0Y116/EE2BEG2",
"pin": "B8",
- "wire": "VBRK_X29Y129/VBRK_NE2A3"
+ "wire": "VBRK_X9Y121/VBRK_EE2A2",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3",
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_SE4C0_9",
+ "CMT_FIFO_R_X7Y124/CMT_FIFO_WW2A0_3",
+ "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0",
+ "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SE4C0_6",
+ "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_WW2A0_0",
+ "HCLK_R_X5Y130/HCLK_SE6C0",
+ "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2",
+ "INT_INTERFACE_R_X1Y116/INT_INTERFACE_WW2A0",
+ "INT_INTERFACE_R_X1Y122/INT_INTERFACE_SE4C0",
+ "INT_L_X0Y116/EE2BEG2",
+ "INT_L_X0Y116/ER1END2",
+ "INT_L_X0Y116/WR1BEG2",
+ "INT_L_X0Y116/WW2END0",
+ "INT_L_X0Y126/LOGIC_OUTS_L18",
+ "INT_L_X0Y126/SE6BEG0",
+ "INT_R_X1Y116/EE2A2",
+ "INT_R_X1Y116/WW2A0",
+ "INT_R_X1Y122/SE6E0",
+ "INT_R_X1Y123/SE6D0",
+ "INT_R_X1Y124/SE6C0",
+ "INT_R_X1Y125/SE6B0",
+ "INT_R_X1Y126/SE6A0",
+ "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_ER1BEG2",
+ "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_WR1END2",
+ "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_LOGIC_OUTS_L18",
+ "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_LOGIC_OUTS_L_B18",
+ "LIOB33_X0Y125/IOB_IBUF0",
+ "LIOI3_X0Y125/IOI_ILOGIC0_O",
+ "LIOI3_X0Y125/IOI_LOGIC_OUTS18_1",
+ "LIOI3_X0Y125/LIOI_I0",
+ "LIOI3_X0Y125/LIOI_IBUF0",
+ "LIOI3_X0Y125/LIOI_ILOGIC0_D",
+ "L_TERM_INT_X2Y121/L_TERM_INT_WR1BEG3",
+ "L_TERM_INT_X2Y132/TERM_INT_LOGIC_OUTS_L_B18",
+ "VBRK_X9Y121/VBRK_EE2A2",
+ "VBRK_X9Y121/VBRK_WW2A0",
+ "VBRK_X9Y127/VBRK_SE4C0"
+ ]
},
{
"name": "dout[0]",
- "node": "INT_R_X17Y125/SE6BEG0",
+ "node": "INT_R_X23Y133/LH12",
"pin": "H5",
- "wire": ""
+ "wire": "VBRK_X61Y139/VBRK_LH12",
+ "wires_outside_roi": [
+ "BRAM_INT_INTERFACE_L_X30Y133/INT_INTERFACE_LH6",
+ "BRAM_L_X30Y130/BRAM_LH6_3",
+ "CLBLL_L_X24Y133/CLBLL_LH12",
+ "CLBLL_L_X26Y133/CLBLL_LH10",
+ "CLBLL_L_X28Y133/CLBLL_LH8",
+ "CLBLL_R_X31Y133/CLBLL_LH4",
+ "CLBLM_L_X32Y133/CLBLM_LH4",
+ "CLBLM_R_X25Y133/CLBLM_LH10",
+ "CLBLM_R_X27Y133/CLBLM_LH8",
+ "CLBLM_R_X29Y133/CLBLM_LH6",
+ "CLBLM_R_X33Y133/CLBLM_LH2",
+ "CLK_FEED_X60Y139/CLK_FEED_LH12",
+ "DSP_L_X34Y130/DSP_LH2_3",
+ "INT_INTERFACE_L_X34Y133/INT_INTERFACE_LH2",
+ "INT_INTERFACE_R_X23Y133/INT_INTERFACE_LH12",
+ "INT_L_X24Y133/LH11",
+ "INT_L_X26Y133/LH9",
+ "INT_L_X28Y133/LH7",
+ "INT_L_X30Y133/LH5",
+ "INT_L_X32Y133/LH3",
+ "INT_L_X34Y133/LH1",
+ "INT_R_X25Y133/LH10",
+ "INT_R_X27Y133/LH8",
+ "INT_R_X29Y133/LH6",
+ "INT_R_X31Y133/LH4",
+ "INT_R_X33Y133/LH2",
+ "INT_R_X35Y133/LH0",
+ "VBRK_X61Y139/VBRK_LH12",
+ "VBRK_X66Y139/VBRK_LH10",
+ "VBRK_X80Y139/VBRK_LH4",
+ "VBRK_X85Y139/VBRK_LH2"
+ ]
},
{
"name": "dout[1]",
- "node": "INT_R_X17Y128/SE6BEG0",
+ "node": "INT_R_X23Y135/LH12",
"pin": "J5",
- "wire": ""
+ "wire": "VBRK_X61Y141/VBRK_LH12",
+ "wires_outside_roi": [
+ "BRAM_INT_INTERFACE_L_X30Y135/INT_INTERFACE_LH6",
+ "BRAM_L_X30Y135/BRAM_LH6_0",
+ "CLBLL_L_X24Y135/CLBLL_LH12",
+ "CLBLL_L_X26Y135/CLBLL_LH10",
+ "CLBLL_L_X28Y135/CLBLL_LH8",
+ "CLBLL_R_X31Y135/CLBLL_LH4",
+ "CLBLM_L_X32Y135/CLBLM_LH4",
+ "CLBLM_R_X25Y135/CLBLM_LH10",
+ "CLBLM_R_X27Y135/CLBLM_LH8",
+ "CLBLM_R_X29Y135/CLBLM_LH6",
+ "CLBLM_R_X33Y135/CLBLM_LH2",
+ "CLK_FEED_X60Y141/CLK_FEED_LH12",
+ "DSP_L_X34Y135/DSP_LH2_0",
+ "INT_INTERFACE_L_X34Y135/INT_INTERFACE_LH2",
+ "INT_INTERFACE_R_X23Y135/INT_INTERFACE_LH12",
+ "INT_L_X24Y135/LH11",
+ "INT_L_X26Y135/LH9",
+ "INT_L_X28Y135/LH7",
+ "INT_L_X30Y135/LH5",
+ "INT_L_X32Y135/LH3",
+ "INT_L_X34Y135/LH1",
+ "INT_R_X25Y135/LH10",
+ "INT_R_X27Y135/LH8",
+ "INT_R_X29Y135/LH6",
+ "INT_R_X31Y135/LH4",
+ "INT_R_X33Y135/LH2",
+ "INT_R_X35Y135/LH0",
+ "VBRK_X61Y141/VBRK_LH12",
+ "VBRK_X66Y141/VBRK_LH10",
+ "VBRK_X80Y141/VBRK_LH4",
+ "VBRK_X85Y141/VBRK_LH2"
+ ]
},
{
"name": "dout[2]",
- "node": "INT_L_X10Y131/SW6BEG0",
+ "node": "INT_L_X2Y133/SW6BEG0",
"pin": "T9",
- "wire": "VBRK_X29Y137/VBRK_SW4A0"
+ "wire": "VBRK_X9Y139/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8",
+ "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_8",
+ "INT_INTERFACE_R_X1Y133/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y129/SW6END0",
+ "INT_R_X1Y129/SW6E0",
+ "INT_R_X1Y130/SW6D0",
+ "INT_R_X1Y131/SW6C0",
+ "INT_R_X1Y132/SW6B0",
+ "INT_R_X1Y133/SW6A0",
+ "VBRK_X9Y139/VBRK_SW4A0"
+ ]
},
{
"name": "dout[3]",
- "node": "INT_L_X10Y134/SW6BEG0",
+ "node": "INT_L_X2Y135/SW6BEG0",
"pin": "T10",
- "wire": "VBRK_X29Y140/VBRK_SW4A0"
+ "wire": "VBRK_X9Y141/VBRK_SW4A0",
+ "wires_outside_roi": [
+ "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_10",
+ "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_10",
+ "INT_INTERFACE_R_X1Y135/INT_INTERFACE_SW4A0",
+ "INT_L_X0Y131/SW6END0",
+ "INT_R_X1Y131/SW6E0",
+ "INT_R_X1Y132/SW6D0",
+ "INT_R_X1Y133/SW6C0",
+ "INT_R_X1Y134/SW6B0",
+ "INT_R_X1Y135/SW6A0",
+ "VBRK_X9Y141/VBRK_SW4A0"
+ ]
},
{
"name": "dout[4]",
- "node": "INT_R_X17Y137/SE6BEG0",
+ "node": "INT_R_X23Y137/LH12",
"pin": "F6",
- "wire": ""
+ "wire": "VBRK_X61Y143/VBRK_LH12",
+ "wires_outside_roi": [
+ "BRAM_INT_INTERFACE_L_X30Y137/INT_INTERFACE_LH6",
+ "BRAM_L_X30Y135/BRAM_LH6_2",
+ "CLBLL_L_X24Y137/CLBLL_LH12",
+ "CLBLL_L_X26Y137/CLBLL_LH10",
+ "CLBLL_L_X28Y137/CLBLL_LH8",
+ "CLBLL_R_X31Y137/CLBLL_LH4",
+ "CLBLM_L_X32Y137/CLBLM_LH4",
+ "CLBLM_R_X25Y137/CLBLM_LH10",
+ "CLBLM_R_X27Y137/CLBLM_LH8",
+ "CLBLM_R_X29Y137/CLBLM_LH6",
+ "CLBLM_R_X33Y137/CLBLM_LH2",
+ "CLK_BUFG_REBUF_X60Y142/CLK_BUFG_REBUF_LH12_1",
+ "DSP_L_X34Y135/DSP_LH2_2",
+ "INT_INTERFACE_L_X34Y137/INT_INTERFACE_LH2",
+ "INT_INTERFACE_R_X23Y137/INT_INTERFACE_LH12",
+ "INT_L_X24Y137/LH11",
+ "INT_L_X26Y137/LH9",
+ "INT_L_X28Y137/LH7",
+ "INT_L_X30Y137/LH5",
+ "INT_L_X32Y137/LH3",
+ "INT_L_X34Y137/LH1",
+ "INT_R_X25Y137/LH10",
+ "INT_R_X27Y137/LH8",
+ "INT_R_X29Y137/LH6",
+ "INT_R_X31Y137/LH4",
+ "INT_R_X33Y137/LH2",
+ "INT_R_X35Y137/LH0",
+ "VBRK_X61Y143/VBRK_LH12",
+ "VBRK_X66Y143/VBRK_LH10",
+ "VBRK_X80Y143/VBRK_LH4",
+ "VBRK_X85Y143/VBRK_LH2"
+ ]
},
{
"name": "dout[5]",
- "node": "INT_R_X17Y140/SE6BEG0",
+ "node": "INT_R_X23Y139/LH12",
"pin": "J4",
- "wire": ""
+ "wire": "VBRK_X61Y145/VBRK_LH12",
+ "wires_outside_roi": [
+ "BRAM_INT_INTERFACE_L_X30Y139/INT_INTERFACE_LH6",
+ "BRAM_L_X30Y135/BRAM_LH6_4",
+ "CLBLL_L_X24Y139/CLBLL_LH12",
+ "CLBLL_L_X26Y139/CLBLL_LH10",
+ "CLBLL_L_X28Y139/CLBLL_LH8",
+ "CLBLL_R_X31Y139/CLBLL_LH4",
+ "CLBLM_L_X32Y139/CLBLM_LH4",
+ "CLBLM_R_X25Y139/CLBLM_LH10",
+ "CLBLM_R_X27Y139/CLBLM_LH8",
+ "CLBLM_R_X29Y139/CLBLM_LH6",
+ "CLBLM_R_X33Y139/CLBLM_LH2",
+ "CLK_FEED_X60Y145/CLK_FEED_LH12",
+ "DSP_L_X34Y135/DSP_LH2_4",
+ "INT_INTERFACE_L_X34Y139/INT_INTERFACE_LH2",
+ "INT_INTERFACE_R_X23Y139/INT_INTERFACE_LH12",
+ "INT_L_X24Y139/LH11",
+ "INT_L_X26Y139/LH9",
+ "INT_L_X28Y139/LH7",
+ "INT_L_X30Y139/LH5",
+ "INT_L_X32Y139/LH3",
+ "INT_L_X34Y139/LH1",
+ "INT_R_X25Y139/LH10",
+ "INT_R_X27Y139/LH8",
+ "INT_R_X29Y139/LH6",
+ "INT_R_X31Y139/LH4",
+ "INT_R_X33Y139/LH2",
+ "INT_R_X35Y139/LH0",
+ "VBRK_X61Y145/VBRK_LH12",
+ "VBRK_X66Y145/VBRK_LH10",
+ "VBRK_X80Y145/VBRK_LH4",
+ "VBRK_X85Y145/VBRK_LH2"
+ ]
},
{
"name": "dout[6]",
- "node": "INT_R_X17Y143/SE6BEG0",
+ "node": "INT_R_X23Y141/LH12",
"pin": "J2",
- "wire": ""
+ "wire": "VBRK_X61Y147/VBRK_LH12",
+ "wires_outside_roi": [
+ "BRAM_INT_INTERFACE_L_X30Y141/INT_INTERFACE_LH6",
+ "BRAM_L_X30Y140/BRAM_LH6_1",
+ "CLBLL_L_X24Y141/CLBLL_LH12",
+ "CLBLL_L_X26Y141/CLBLL_LH10",
+ "CLBLL_L_X28Y141/CLBLL_LH8",
+ "CLBLL_R_X31Y141/CLBLL_LH4",
+ "CLBLM_L_X32Y141/CLBLM_LH4",
+ "CLBLM_R_X25Y141/CLBLM_LH10",
+ "CLBLM_R_X27Y141/CLBLM_LH8",
+ "CLBLM_R_X29Y141/CLBLM_LH6",
+ "CLBLM_R_X33Y141/CLBLM_LH2",
+ "CLK_FEED_X60Y147/CLK_FEED_LH12",
+ "DSP_L_X34Y140/DSP_LH2_1",
+ "INT_INTERFACE_L_X34Y141/INT_INTERFACE_LH2",
+ "INT_INTERFACE_R_X23Y141/INT_INTERFACE_LH12",
+ "INT_L_X24Y141/LH11",
+ "INT_L_X26Y141/LH9",
+ "INT_L_X28Y141/LH7",
+ "INT_L_X30Y141/LH5",
+ "INT_L_X32Y141/LH3",
+ "INT_L_X34Y141/LH1",
+ "INT_R_X25Y141/LH10",
+ "INT_R_X27Y141/LH8",
+ "INT_R_X29Y141/LH6",
+ "INT_R_X31Y141/LH4",
+ "INT_R_X33Y141/LH2",
+ "INT_R_X35Y141/LH0",
+ "VBRK_X61Y147/VBRK_LH12",
+ "VBRK_X66Y147/VBRK_LH10",
+ "VBRK_X80Y147/VBRK_LH4",
+ "VBRK_X85Y147/VBRK_LH2"
+ ]
},
{
"name": "dout[7]",
- "node": "INT_R_X17Y146/SE6BEG0",
+ "node": "INT_R_X23Y143/LH12",
"pin": "H6",
- "wire": ""
+ "wire": "VBRK_X61Y149/VBRK_LH12",
+ "wires_outside_roi": [
+ "BRAM_INT_INTERFACE_L_X30Y143/INT_INTERFACE_LH6",
+ "BRAM_L_X30Y140/BRAM_LH6_3",
+ "CLBLL_L_X24Y143/CLBLL_LH12",
+ "CLBLL_L_X26Y143/CLBLL_LH10",
+ "CLBLL_L_X28Y143/CLBLL_LH8",
+ "CLBLL_R_X31Y143/CLBLL_LH4",
+ "CLBLM_L_X32Y143/CLBLM_LH4",
+ "CLBLM_R_X25Y143/CLBLM_LH10",
+ "CLBLM_R_X27Y143/CLBLM_LH8",
+ "CLBLM_R_X29Y143/CLBLM_LH6",
+ "CLBLM_R_X33Y143/CLBLM_LH2",
+ "CLK_FEED_X60Y149/CLK_FEED_LH12",
+ "DSP_L_X34Y140/DSP_LH2_3",
+ "INT_INTERFACE_L_X34Y143/INT_INTERFACE_LH2",
+ "INT_INTERFACE_R_X23Y143/INT_INTERFACE_LH12",
+ "INT_L_X24Y143/LH11",
+ "INT_L_X26Y143/LH9",
+ "INT_L_X28Y143/LH7",
+ "INT_L_X30Y143/LH5",
+ "INT_L_X32Y143/LH3",
+ "INT_L_X34Y143/LH1",
+ "INT_R_X25Y143/LH10",
+ "INT_R_X27Y143/LH8",
+ "INT_R_X29Y143/LH6",
+ "INT_R_X31Y143/LH4",
+ "INT_R_X33Y143/LH2",
+ "INT_R_X35Y143/LH0",
+ "VBRK_X61Y149/VBRK_LH12",
+ "VBRK_X66Y149/VBRK_LH10",
+ "VBRK_X80Y149/VBRK_LH4",
+ "VBRK_X85Y149/VBRK_LH2"
+ ]
}
+ ],
+ "required_features": [
+ "",
+ "CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
+ "CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y142.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y38.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
+ "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
+ "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O",
+ "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
+ "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
+ "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK16",
+ "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_CK_IN_R0_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
+ "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
+ "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
+ "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+ "INT_L_X0Y1.IMUX_L34.WW2END0",
+ "INT_L_X0Y102.EE2BEG2.SS6END2",
+ "INT_L_X0Y104.EE2BEG2.ER1END2",
+ "INT_L_X0Y104.WR1BEG2.NN6END1",
+ "INT_L_X0Y106.EE2BEG2.SS6END2",
+ "INT_L_X0Y107.LV_L18.LV_L0",
+ "INT_L_X0Y108.EE2BEG2.EL1END2",
+ "INT_L_X0Y108.LVB_L12.LV_L0",
+ "INT_L_X0Y108.SS6BEG2.LVB_L12",
+ "INT_L_X0Y108.WL1BEG2.SL1END3",
+ "INT_L_X0Y109.SL1BEG3.EL1END3",
+ "INT_L_X0Y11.SE6BEG0.SS6END0",
+ "INT_L_X0Y110.EE2BEG2.ER1END2",
+ "INT_L_X0Y110.NW6BEG0.LV_L0",
+ "INT_L_X0Y110.WL1BEG_N3.SS6END0",
+ "INT_L_X0Y110.WR1BEG2.WW2END0",
+ "INT_L_X0Y111.LV_L18.LV_L0",
+ "INT_L_X0Y112.EE2BEG2.SE6END2",
+ "INT_L_X0Y112.SS6BEG2.LVB_L0",
+ "INT_L_X0Y113.LV_L18.LV_L0",
+ "INT_L_X0Y114.EE2BEG2.EL1END2",
+ "INT_L_X0Y114.WL1BEG2.NW2END_S0_0",
+ "INT_L_X0Y116.EE2BEG2.ER1END2",
+ "INT_L_X0Y116.SS6BEG0.SS6END0",
+ "INT_L_X0Y116.WR1BEG2.WW2END0",
+ "INT_L_X0Y120.SE6BEG0.LV_L0",
+ "INT_L_X0Y122.SS6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y123.NL1BEG_N3.LOGIC_OUTS_L18",
+ "INT_L_X0Y123.NR1BEG3.NL1BEG_N3",
+ "INT_L_X0Y124.LVB_L12.NR1END3",
+ "INT_L_X0Y124.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y125.LV_L18.NR1END0",
+ "INT_L_X0Y125.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y126.LV_L18.NR1END0",
+ "INT_L_X0Y126.SE6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y127.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y128.EL1BEG_N3.LOGIC_OUTS_L18",
+ "INT_L_X0Y128.LV_L18.NR1END0",
+ "INT_L_X0Y129.LV_L18.SW6END0",
+ "INT_L_X0Y131.LV_L18.SW6END0",
+ "INT_L_X0Y137.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y138.LV_L18.NR1END0",
+ "INT_L_X0Y15.SS6BEG0.SS6END0",
+ "INT_L_X0Y17.SS6BEG0.SS6END0",
+ "INT_L_X0Y2.FAN_ALT1.EL1END3",
+ "INT_L_X0Y2.IMUX_L34.FAN_BOUNCE1",
+ "INT_L_X0Y21.SS6BEG0.LV_L0",
+ "INT_L_X0Y23.SS6BEG0.LV_L0",
+ "INT_L_X0Y3.WL1BEG_N3.SS6END0",
+ "INT_L_X0Y39.LV_L18.LV_L0",
+ "INT_L_X0Y41.LV_L18.LV_L0",
+ "INT_L_X0Y57.LV_L18.LV_L0",
+ "INT_L_X0Y59.LV_L18.LV_L0",
+ "INT_L_X0Y75.LV_L18.LV_L0",
+ "INT_L_X0Y77.LV_L18.LV_L0",
+ "INT_L_X0Y9.SS6BEG0.SS6END0",
+ "INT_L_X0Y93.LV_L18.LV_L0",
+ "INT_L_X0Y95.LV_L18.LV_L0",
+ "INT_L_X0Y98.NN6BEG1.LV_L9",
+ "INT_L_X2Y1.WW2BEG0.SS6END0",
+ "INT_L_X2Y7.SS6BEG0.SE6END0",
+ "INT_L_X40Y52.EE4BEG0.SE2END0",
+ "INT_L_X40Y60.SE6BEG0.SE2END0",
+ "INT_L_X42Y51.SE2BEG1.ER1END1",
+ "INT_L_X42Y56.ER1BEG1.SE6END0",
+ "INT_L_X42Y59.SE2BEG1.ER1END1",
+ "INT_R_X1Y114.NW2BEG0.NE6END0",
+ "INT_R_X1Y116.SW6BEG2.LVB0",
+ "INT_R_X1Y127.NR1BEG3.EL1END3",
+ "INT_R_X1Y128.LVB12.NR1END3",
+ "INT_R_X35Y101.LV18.LV0",
+ "INT_R_X35Y103.LV18.LV0",
+ "INT_R_X35Y105.LV18.LV0",
+ "INT_R_X35Y107.LV18.LV0",
+ "INT_R_X35Y115.LV18.LV0",
+ "INT_R_X35Y117.LV18.LV0",
+ "INT_R_X35Y119.LV18.LV0",
+ "INT_R_X35Y121.LV18.LV0",
+ "INT_R_X35Y123.LV18.LV0",
+ "INT_R_X35Y125.LV18.LV0",
+ "INT_R_X35Y133.LV18.LH0",
+ "INT_R_X35Y135.LV18.LH0",
+ "INT_R_X35Y137.LV18.LH0",
+ "INT_R_X35Y139.LV18.LH0",
+ "INT_R_X35Y141.LV18.LH0",
+ "INT_R_X35Y143.LV18.LH0",
+ "INT_R_X35Y53.EE4BEG0.LV0",
+ "INT_R_X35Y61.SE6BEG0.LV0",
+ "INT_R_X35Y63.SE6BEG0.LV0",
+ "INT_R_X35Y67.SE6BEG0.LV0",
+ "INT_R_X35Y69.SE6BEG0.LV0",
+ "INT_R_X35Y71.LV18.LV0",
+ "INT_R_X35Y79.LV18.LV0",
+ "INT_R_X35Y81.LV18.LV0",
+ "INT_R_X35Y83.EE4BEG0.LV0",
+ "INT_R_X35Y85.LV18.LV0",
+ "INT_R_X35Y87.LV18.LV0",
+ "INT_R_X35Y89.LV18.LV0",
+ "INT_R_X35Y97.LV18.LV0",
+ "INT_R_X35Y99.LV18.LV0",
+ "INT_R_X37Y57.SE6BEG0.SE6END0",
+ "INT_R_X37Y59.SE6BEG0.SE6END0",
+ "INT_R_X37Y63.SE6BEG0.SE6END0",
+ "INT_R_X37Y65.SE6BEG0.SE6END0",
+ "INT_R_X39Y53.EE4BEG0.EE4END0",
+ "INT_R_X39Y53.SE2BEG0.SE6END0",
+ "INT_R_X39Y55.SE6BEG0.SE6END0",
+ "INT_R_X39Y59.EE2BEG0.SE6END0",
+ "INT_R_X39Y61.SE2BEG0.SE6END0",
+ "INT_R_X39Y83.SE6BEG0.EE4END0",
+ "INT_R_X41Y51.ER1BEG1.SE6END0",
+ "INT_R_X41Y59.ER1BEG1.EE2END0",
+ "INT_R_X41Y73.SE6BEG0.SS6END0",
+ "INT_R_X41Y79.SS6BEG0.SE6END0",
+ "INT_R_X43Y50.IMUX34.SE2END1",
+ "INT_R_X43Y51.IMUX34.SR1BEG_S0",
+ "INT_R_X43Y51.SR1BEG_S0.WW4END_S0_0",
+ "INT_R_X43Y52.IMUX34.SR1BEG_S0",
+ "INT_R_X43Y52.SR1BEG_S0.WL1END3",
+ "INT_R_X43Y53.EL1BEG_N3.EE4END0",
+ "INT_R_X43Y55.IMUX34.SL1END1",
+ "INT_R_X43Y56.SL1BEG1.ER1END1",
+ "INT_R_X43Y58.IMUX34.SE2END1",
+ "INT_R_X43Y61.IMUX34.SL1END1",
+ "INT_R_X43Y62.SL1BEG1.SR1END1",
+ "INT_R_X43Y63.SR1BEG1.SS6END0",
+ "INT_R_X43Y69.SS6BEG0.SE6END0",
+ "LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y1.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y1.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y121.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y121.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y121.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y121.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y121.IOB_Y1.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y123.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y123.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y123.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y123.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y123.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y123.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y123.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y123.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y123.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y123.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y123.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y123.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y125.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y125.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y125.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y125.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y125.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y125.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y125.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y125.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y125.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y125.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y125.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y125.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y127.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y127.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y127.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y127.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y127.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y127.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y127.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y127.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y127.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y127.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y127.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y127.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y137.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y137.IOB_Y0.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y137.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y137.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y137.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y137.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y137.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y137.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y137.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
+ "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
+ "RIOB33_SING_X43Y50.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_SING_X43Y50.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_SING_X43Y50.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_SING_X43Y50.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_SING_X43Y50.IOB_Y0.SLEW.SLOW",
+ "RIOB33_X43Y51.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y51.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y51.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y51.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y51.IOB_Y0.SLEW.SLOW",
+ "RIOB33_X43Y51.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y51.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y51.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y51.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y51.IOB_Y1.SLEW.SLOW",
+ "RIOB33_X43Y55.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y55.IOB_Y0.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y55.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y55.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y55.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y55.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y55.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y55.IOB_Y1.SLEW.SLOW",
+ "RIOB33_X43Y57.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y57.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y57.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y57.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y57.IOB_Y0.SLEW.SLOW",
+ "RIOB33_X43Y57.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y57.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y57.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y61.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y61.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y61.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y61.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y61.IOB_Y1.SLEW.SLOW",
+ "RIOB33_X43Y75.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y75.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
]
-}
\ No newline at end of file
+}
diff --git a/artix7/harness/arty-a7/swbut/design.txt b/artix7/harness/arty-a7/swbut/design.txt
index e9e91d5..5cfb2dd 100644
--- a/artix7/harness/arty-a7/swbut/design.txt
+++ b/artix7/harness/arty-a7/swbut/design.txt
@@ -1,18 +1,18 @@
name node pin wire
clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 E3 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0
-din[0] INT_R_X9Y102/NE2BEG3 A8 VBRK_X29Y108/VBRK_NE2A3
-din[1] INT_R_X9Y105/NE2BEG3 C11 VBRK_X29Y111/VBRK_NE2A3
-din[2] INT_R_X9Y108/NE2BEG3 C10 VBRK_X29Y114/VBRK_NE2A3
-din[3] INT_R_X9Y111/NE2BEG3 A10 VBRK_X29Y117/VBRK_NE2A3
-din[4] INT_R_X9Y114/NE2BEG3 D9 VBRK_X29Y120/VBRK_NE2A3
-din[5] INT_R_X9Y117/NE2BEG3 C9 VBRK_X29Y123/VBRK_NE2A3
-din[6] INT_R_X9Y120/NE2BEG3 B9 VBRK_X29Y126/VBRK_NE2A3
-din[7] INT_R_X9Y123/NE2BEG3 B8 VBRK_X29Y129/VBRK_NE2A3
-dout[0] INT_R_X17Y125/SE6BEG0 H5
-dout[1] INT_R_X17Y128/SE6BEG0 J5
-dout[2] INT_L_X10Y131/SW6BEG0 T9 VBRK_X29Y137/VBRK_SW4A0
-dout[3] INT_L_X10Y134/SW6BEG0 T10 VBRK_X29Y140/VBRK_SW4A0
-dout[4] INT_R_X17Y137/SE6BEG0 F6
-dout[5] INT_R_X17Y140/SE6BEG0 J4
-dout[6] INT_R_X17Y143/SE6BEG0 J2
-dout[7] INT_R_X17Y146/SE6BEG0 H6
+din[0] INT_L_X0Y102/EE2BEG2 A8 VBRK_X9Y107/VBRK_EE2A2
+din[1] INT_L_X0Y104/EE2BEG2 C11 VBRK_X9Y109/VBRK_EE2A2
+din[2] INT_L_X0Y106/EE2BEG2 C10 VBRK_X9Y111/VBRK_EE2A2
+din[3] INT_L_X0Y108/EE2BEG2 A10 VBRK_X9Y113/VBRK_EE2A2
+din[4] INT_L_X0Y110/EE2BEG2 D9 VBRK_X9Y115/VBRK_EE2A2
+din[5] INT_L_X0Y112/EE2BEG2 C9 VBRK_X9Y117/VBRK_EE2A2
+din[6] INT_L_X0Y114/EE2BEG2 B9 VBRK_X9Y119/VBRK_EE2A2
+din[7] INT_L_X0Y116/EE2BEG2 B8 VBRK_X9Y121/VBRK_EE2A2
+dout[0] INT_R_X23Y133/LH12 H5 VBRK_X61Y139/VBRK_LH12
+dout[1] INT_R_X23Y135/LH12 J5 VBRK_X61Y141/VBRK_LH12
+dout[2] INT_L_X2Y133/SW6BEG0 T9 VBRK_X9Y139/VBRK_SW4A0
+dout[3] INT_L_X2Y135/SW6BEG0 T10 VBRK_X9Y141/VBRK_SW4A0
+dout[4] INT_R_X23Y137/LH12 F6 VBRK_X61Y143/VBRK_LH12
+dout[5] INT_R_X23Y139/LH12 J4 VBRK_X61Y145/VBRK_LH12
+dout[6] INT_R_X23Y141/LH12 J2 VBRK_X61Y147/VBRK_LH12
+dout[7] INT_R_X23Y143/LH12 H6 VBRK_X61Y149/VBRK_LH12
diff --git a/artix7/harness/arty-a7/uart/design.bit b/artix7/harness/arty-a7/uart/design.bit
index 7aca898..9d9416f 100644
--- a/artix7/harness/arty-a7/uart/design.bit
+++ b/artix7/harness/arty-a7/uart/design.bit
Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.dcp b/artix7/harness/arty-a7/uart/design.dcp
index 6a838ac..821fb1c 100644
--- a/artix7/harness/arty-a7/uart/design.dcp
+++ b/artix7/harness/arty-a7/uart/design.dcp
Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.json b/artix7/harness/arty-a7/uart/design.json
index 9d4f505..70ef5f0 100644
--- a/artix7/harness/arty-a7/uart/design.json
+++ b/artix7/harness/arty-a7/uart/design.json
@@ -252,9 +252,143 @@
"CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y142.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y38.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
+ "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
+ "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_BELOW",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
+ "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK16",
- "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE"
+ "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_CK_IN_R0_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
+ "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
+ "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
+ "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+ "INT_L_X0Y1.IMUX_L34.SL1END1",
+ "INT_L_X0Y102.EE2BEG2.SE2END2",
+ "INT_L_X0Y103.SW2BEG2.SE6END2",
+ "INT_L_X0Y105.LV_L18.LV_L0",
+ "INT_L_X0Y111.IMUX_L34.SL1END1",
+ "INT_L_X0Y112.SL1BEG1.SR1END1",
+ "INT_L_X0Y113.SR1BEG1.SS6END0",
+ "INT_L_X0Y119.SS6BEG0.SS6END0",
+ "INT_L_X0Y120.SE2BEG3.EL1END3",
+ "INT_L_X0Y121.WL1BEG_N3.LOGIC_OUTS_L18",
+ "INT_L_X0Y123.LV_L18.LV_L0",
+ "INT_L_X0Y125.SS6BEG0.LV_L0",
+ "INT_L_X0Y141.LV_L18.SW6END0",
+ "INT_L_X0Y143.LV_L18.SW6END0",
+ "INT_L_X0Y15.SS6BEG0.LV_L0",
+ "INT_L_X0Y2.SL1BEG1.SR1END1",
+ "INT_L_X0Y3.SR1BEG1.SS6END0",
+ "INT_L_X0Y33.LV_L18.LV_L0",
+ "INT_L_X0Y51.LV_L18.LV_L0",
+ "INT_L_X0Y69.LV_L18.LV_L0",
+ "INT_L_X0Y87.LV_L18.LV_L0",
+ "INT_L_X0Y9.SS6BEG0.SS6END0",
+ "INT_R_X1Y107.SW6BEG2.LVB0",
+ "INT_R_X1Y119.LVB12.SE2END3",
+ "INT_R_X25Y123.NL1BEG2.WW4END3",
+ "INT_R_X25Y124.NN2BEG2.NL1END2",
+ "INT_R_X25Y126.WW2BEG1.NN2END2",
+ "INT_R_X31Y105.LV0.LV18",
+ "INT_R_X31Y123.WW4BEG3.LV18",
+ "INT_R_X31Y87.LV0.LH12",
+ "INT_R_X43Y68.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y69.LV0.NR1END0",
+ "INT_R_X43Y87.LH0.LV18",
+ "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y1.IOB_Y0.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y1.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y111.IOB_Y0.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y121.IOB_Y0.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y121.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y121.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y121.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y121.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
+ "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y67.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y67.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y67.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y67.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y67.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y67.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y67.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y67.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y67.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y75.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y75.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
]
}
diff --git a/artix7/harness/basys3/swbut/design.bit b/artix7/harness/basys3/swbut/design.bit
index 7296a39..5e186b6 100644
--- a/artix7/harness/basys3/swbut/design.bit
+++ b/artix7/harness/basys3/swbut/design.bit
Binary files differ
diff --git a/artix7/harness/basys3/swbut/design.dcp b/artix7/harness/basys3/swbut/design.dcp
index 19cf84d..59ed01a 100644
--- a/artix7/harness/basys3/swbut/design.dcp
+++ b/artix7/harness/basys3/swbut/design.dcp
Binary files differ
diff --git a/artix7/harness/basys3/swbut/design.json b/artix7/harness/basys3/swbut/design.json
index 135bad9..7856957 100644
--- a/artix7/harness/basys3/swbut/design.json
+++ b/artix7/harness/basys3/swbut/design.json
@@ -2,7 +2,7 @@
"info": {
"GRID_X_MAX": 58,
"GRID_X_MIN": 10,
- "GRID_Y_MAX": 52,
+ "GRID_Y_MAX": 51,
"GRID_Y_MIN": 0
},
"ports": [
@@ -3060,13 +3060,628 @@
}
],
"required_features": [
+ "",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
+ "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_BOT_R_CK_MUXED0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
+ "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O",
"CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
"CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_ABOVE",
"CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_BELOW",
"CLK_BUFG_REBUF_X60Y142.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y38.GCLK0_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
+ "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_BELOW",
+ "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
+ "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_ABOVE",
+ "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_BELOW",
+ "CLK_HROW_BOT_R_X60Y26.CLK_HROW_BOT_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
+ "CLK_HROW_BOT_R_X60Y26.CLK_HROW_CK_IN_R0_ACTIVE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
"CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
"CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0",
- "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE"
+ "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
+ "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
+ "HCLK_CMT_L_X106Y26.HCLK_CMT_CCIO0_ACTIVE",
+ "HCLK_CMT_L_X106Y26.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
+ "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
+ "INT_L_X0Y0.IMUX_L34.SS2END1",
+ "INT_L_X0Y1.IMUX_L34.WW2END0",
+ "INT_L_X0Y10.LV_L0.NR1END0",
+ "INT_L_X0Y10.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y100.NN6BEG3.LV_L18",
+ "INT_L_X0Y101.LVB_L12.LV_L0",
+ "INT_L_X0Y101.NN6BEG3.LV_L18",
+ "INT_L_X0Y102.EE2BEG2.NN6END2",
+ "INT_L_X0Y103.LV_L18.LV_L0",
+ "INT_L_X0Y103.NR1BEG2.NN6END2",
+ "INT_L_X0Y104.EE2BEG2.NR1END2",
+ "INT_L_X0Y104.NN6BEG2.LVB_L12",
+ "INT_L_X0Y105.LV_L18.LV_L0",
+ "INT_L_X0Y105.NN6BEG3.NN6END3",
+ "INT_L_X0Y106.EE2BEG2.EL1END2",
+ "INT_L_X0Y106.NR1BEG3.NN6END3",
+ "INT_L_X0Y106.WL1BEG2.SR1END3",
+ "INT_L_X0Y107.LV_L18.LV_L0",
+ "INT_L_X0Y107.NL1BEG2.NR1END3",
+ "INT_L_X0Y107.SR1BEG3.NN6END3",
+ "INT_L_X0Y108.EE2BEG2.NL1END2",
+ "INT_L_X0Y108.NN6BEG2.LVB_L12",
+ "INT_L_X0Y109.LV_L18.LV_L0",
+ "INT_L_X0Y109.NN6BEG2.LVB_L12",
+ "INT_L_X0Y11.LV_L0.NR1END0",
+ "INT_L_X0Y11.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y110.EE2BEG2.NN6END2",
+ "INT_L_X0Y111.IMUX_L34.WR1END1",
+ "INT_L_X0Y111.LV_L18.SW6END0",
+ "INT_L_X0Y111.NL1BEG2.NN6END3",
+ "INT_L_X0Y111.WW2BEG0.SS6END0",
+ "INT_L_X0Y112.EE2BEG2.NL1END2",
+ "INT_L_X0Y112.NW6BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y113.LV_L18.SW6END0",
+ "INT_L_X0Y114.EE2BEG2.NN6END2",
+ "INT_L_X0Y115.LV_L18.SW6END0",
+ "INT_L_X0Y115.NR1BEG2.NN6END2",
+ "INT_L_X0Y116.EE2BEG2.NR1END2",
+ "INT_L_X0Y117.LV_L18.SW6END0",
+ "INT_L_X0Y117.SS6BEG0.SS6END0",
+ "INT_L_X0Y118.EE2BEG2.EL1END2",
+ "INT_L_X0Y118.WL1BEG2.NW2END_S0_0",
+ "INT_L_X0Y119.LV_L18.SW6END0",
+ "INT_L_X0Y12.LV_L0.NR1END0",
+ "INT_L_X0Y12.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y121.LV_L18.SW6END0",
+ "INT_L_X0Y123.LV_L18.SW6END0",
+ "INT_L_X0Y123.SS6BEG0.SS6END0",
+ "INT_L_X0Y125.LV_L18.SW6END0",
+ "INT_L_X0Y127.LV_L18.SW6END0",
+ "INT_L_X0Y129.SS6BEG0.SW6END0",
+ "INT_L_X0Y13.LV_L0.NR1END0",
+ "INT_L_X0Y13.SE6BEG0.SS2END0",
+ "INT_L_X0Y13.SS6BEG0.SS6END0",
+ "INT_L_X0Y15.SS2BEG0.SS6END0",
+ "INT_L_X0Y15.SS6BEG0.LV_L0",
+ "INT_L_X0Y17.NR1BEG1.EL1END1",
+ "INT_L_X0Y17.SE6BEG0.LV_L0",
+ "INT_L_X0Y17.WL1BEG1.SS6END2",
+ "INT_L_X0Y18.IMUX_L34.NR1END1",
+ "INT_L_X0Y19.FAN_ALT1.SS2END2",
+ "INT_L_X0Y19.IMUX_L34.FAN_BOUNCE1",
+ "INT_L_X0Y19.SS6BEG0.LV_L0",
+ "INT_L_X0Y2.IMUX_L34.SS2END1",
+ "INT_L_X0Y2.SS2BEG1.SR1END1",
+ "INT_L_X0Y20.FAN_ALT1.EL1END3",
+ "INT_L_X0Y20.IMUX_L34.FAN_BOUNCE1",
+ "INT_L_X0Y21.SS2BEG2.SS6END2",
+ "INT_L_X0Y21.SS6BEG0.LV_L0",
+ "INT_L_X0Y21.WL1BEG_N3.SS6END0",
+ "INT_L_X0Y23.SS6BEG2.SS6END2",
+ "INT_L_X0Y24.LV_L0.LV_L18",
+ "INT_L_X0Y25.LV_L0.LV_L18",
+ "INT_L_X0Y26.LV_L0.LV_L18",
+ "INT_L_X0Y27.LV_L0.LV_L18",
+ "INT_L_X0Y27.SS6BEG0.SS6END0",
+ "INT_L_X0Y27.SS6BEG2.SS6END2",
+ "INT_L_X0Y28.LV_L0.LV_L18",
+ "INT_L_X0Y29.LV_L0.LV_L18",
+ "INT_L_X0Y29.SS6BEG2.SS6END2",
+ "INT_L_X0Y3.IMUX_L34.WW2END0",
+ "INT_L_X0Y3.SR1BEG1.SS6END0",
+ "INT_L_X0Y30.LV_L0.LV_L18",
+ "INT_L_X0Y31.LV_L0.LV_L18",
+ "INT_L_X0Y33.LV_L18.LV_L0",
+ "INT_L_X0Y33.SS6BEG0.SS6END0",
+ "INT_L_X0Y33.SS6BEG2.SS6END2",
+ "INT_L_X0Y35.LV_L18.LV_L0",
+ "INT_L_X0Y35.SS6BEG2.SS6END2",
+ "INT_L_X0Y37.LV_L18.LV_L0",
+ "INT_L_X0Y39.LV_L18.LV_L0",
+ "INT_L_X0Y39.SS6BEG0.SS6END0",
+ "INT_L_X0Y39.SS6BEG2.SS6END2",
+ "INT_L_X0Y4.IMUX_L34.SR1BEG_S0",
+ "INT_L_X0Y4.SR1BEG_S0.WL1END3",
+ "INT_L_X0Y4.SS2BEG1.SR1END1",
+ "INT_L_X0Y41.SS6BEG2.SS6END2",
+ "INT_L_X0Y42.LV_L0.LV_L18",
+ "INT_L_X0Y43.IMUX_L34.WW2END0",
+ "INT_L_X0Y43.LV_L0.LV_L18",
+ "INT_L_X0Y44.LV_L0.LV_L18",
+ "INT_L_X0Y45.LV_L0.LV_L18",
+ "INT_L_X0Y45.SS6BEG0.SS6END0",
+ "INT_L_X0Y45.SS6BEG2.SS6END2",
+ "INT_L_X0Y46.LV_L0.LV_L18",
+ "INT_L_X0Y47.LV_L0.LV_L18",
+ "INT_L_X0Y47.SS6BEG2.SS6END2",
+ "INT_L_X0Y48.LV_L0.LV_L18",
+ "INT_L_X0Y49.LV_L0.LV_L18",
+ "INT_L_X0Y5.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y5.SR1BEG1.SS2END0",
+ "INT_L_X0Y51.LV_L18.LV_L0",
+ "INT_L_X0Y51.SS6BEG0.SS6END0",
+ "INT_L_X0Y51.SS6BEG2.SS6END2",
+ "INT_L_X0Y53.LV_L18.LV_L0",
+ "INT_L_X0Y53.SE6BEG0.SS6END0",
+ "INT_L_X0Y53.SS6BEG2.SS6END2",
+ "INT_L_X0Y55.LV_L18.LV_L0",
+ "INT_L_X0Y57.LV_L18.LV_L0",
+ "INT_L_X0Y57.SS6BEG0.SS6END0",
+ "INT_L_X0Y57.SS6BEG2.SS6END2",
+ "INT_L_X0Y59.SS6BEG0.LV_L0",
+ "INT_L_X0Y59.SS6BEG2.SS6END2",
+ "INT_L_X0Y6.LV_L0.NR1END0",
+ "INT_L_X0Y6.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y60.LV_L0.LV_L18",
+ "INT_L_X0Y61.LV_L0.LV_L18",
+ "INT_L_X0Y62.LV_L0.LV_L18",
+ "INT_L_X0Y63.LV_L0.LV_L18",
+ "INT_L_X0Y63.SS6BEG0.SS6END0",
+ "INT_L_X0Y63.SS6BEG2.SS6END2",
+ "INT_L_X0Y64.LV_L0.LV_L18",
+ "INT_L_X0Y65.LV_L0.LV_L18",
+ "INT_L_X0Y65.SS6BEG2.SS6END2",
+ "INT_L_X0Y66.LV_L0.LV_L18",
+ "INT_L_X0Y67.LV_L0.LV_L18",
+ "INT_L_X0Y69.LV_L18.LV_L0",
+ "INT_L_X0Y69.SS6BEG0.SS6END0",
+ "INT_L_X0Y69.SS6BEG2.SS6END2",
+ "INT_L_X0Y7.LV_L0.NR1END0",
+ "INT_L_X0Y7.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y7.SS2BEG0.SS6END0",
+ "INT_L_X0Y71.LV_L18.LV_L0",
+ "INT_L_X0Y71.SS6BEG2.SS6END2",
+ "INT_L_X0Y73.LV_L18.LV_L0",
+ "INT_L_X0Y75.LV_L18.LV_L0",
+ "INT_L_X0Y75.SS6BEG0.SS6END0",
+ "INT_L_X0Y75.SS6BEG2.LVB_L0",
+ "INT_L_X0Y77.LV_L18.LV_L0",
+ "INT_L_X0Y77.SS6BEG2.LVB_L0",
+ "INT_L_X0Y77.SW6BEG0.SW6END0",
+ "INT_L_X0Y78.LV_L0.LV_L18",
+ "INT_L_X0Y79.LV_L0.LV_L18",
+ "INT_L_X0Y8.LV_L0.NR1END0",
+ "INT_L_X0Y8.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y80.LVB_L0.LV_L18",
+ "INT_L_X0Y81.LV_L0.LV_L18",
+ "INT_L_X0Y81.SS6BEG0.SW6END0",
+ "INT_L_X0Y82.LV_L0.LV_L18",
+ "INT_L_X0Y83.LV_L0.LV_L18",
+ "INT_L_X0Y84.LVB_L0.LV_L18",
+ "INT_L_X0Y85.LVB_L0.LV_L18",
+ "INT_L_X0Y85.SE6BEG0.LV_L0",
+ "INT_L_X0Y87.LVB_L12.LVB_L0",
+ "INT_L_X0Y87.LV_L18.LV_L0",
+ "INT_L_X0Y89.LVB_L12.LVB_L0",
+ "INT_L_X0Y89.LV_L18.LV_L0",
+ "INT_L_X0Y89.SE6BEG0.SW6END0",
+ "INT_L_X0Y9.LV_L0.NR1END0",
+ "INT_L_X0Y9.NR1BEG0.LOGIC_OUTS_L18",
+ "INT_L_X0Y9.SS6BEG0.SS6END0",
+ "INT_L_X0Y91.LV_L18.LV_L0",
+ "INT_L_X0Y92.LVB_L0.LVB_L12",
+ "INT_L_X0Y93.LV_L18.LV_L0",
+ "INT_L_X0Y95.LV_L18.LV_L0",
+ "INT_L_X0Y96.LVB_L0.LV_L18",
+ "INT_L_X0Y96.NN6BEG2.LVB_L12",
+ "INT_L_X0Y97.LVB_L0.LV_L18",
+ "INT_L_X0Y97.NN6BEG2.LVB_L12",
+ "INT_L_X0Y97.SE6BEG0.LV_L0",
+ "INT_L_X0Y99.LVB_L12.LV_L0",
+ "INT_L_X0Y99.NN6BEG3.LV_L18",
+ "INT_L_X26Y140.WL1BEG1.NW2END3",
+ "INT_L_X2Y1.WW2BEG0.SS6END0",
+ "INT_L_X2Y13.SS6BEG0.SE6END0",
+ "INT_L_X2Y3.WW2BEG0.SS6END0",
+ "INT_L_X2Y43.WW2BEG0.SS6END0",
+ "INT_L_X2Y49.SS6BEG0.SE6END0",
+ "INT_L_X2Y7.SS6BEG0.SS6END0",
+ "INT_L_X2Y81.SW6BEG0.SE6END0",
+ "INT_L_X2Y85.SW6BEG0.SE6END0",
+ "INT_L_X2Y9.SS6BEG0.SE6END0",
+ "INT_L_X2Y93.SW6BEG0.SE6END0",
+ "INT_L_X40Y42.SE6BEG0.SE2END0",
+ "INT_L_X40Y62.EE4BEG0.SE2END0",
+ "INT_L_X40Y80.SE6BEG0.SE2END0",
+ "INT_L_X42Y32.ER1BEG1.SS6END0",
+ "INT_L_X42Y38.SS6BEG0.SE6END0",
+ "INT_L_X42Y39.SE2BEG1.ER1END1",
+ "INT_L_X42Y76.ER1BEG1.SE6END0",
+ "INT_L_X42Y77.SE2BEG1.ER1END1",
+ "INT_R_X1Y11.SS6BEG0.LV0",
+ "INT_R_X1Y111.WR1BEG1.EE2END0",
+ "INT_R_X1Y116.NN2BEG0.NE6END0",
+ "INT_R_X1Y118.NW2BEG0.NN2END0",
+ "INT_R_X1Y29.LV18.LV0",
+ "INT_R_X1Y47.LV18.LV0",
+ "INT_R_X1Y5.WL1BEG_N3.SS6END0",
+ "INT_R_X1Y65.LV18.SW6END0",
+ "INT_R_X1Y73.SE6BEG0.SE6END0",
+ "INT_R_X25Y126.WW2BEG1.WW4END2",
+ "INT_R_X25Y128.WW2BEG1.WW4END2",
+ "INT_R_X25Y130.WW2BEG1.WW4END2",
+ "INT_R_X25Y132.WW2BEG1.WW4END2",
+ "INT_R_X25Y134.WW2BEG1.WW4END2",
+ "INT_R_X25Y135.LV0.LH6",
+ "INT_R_X25Y136.WW2BEG1.WW2END1",
+ "INT_R_X25Y138.WW2BEG1.SS6END1",
+ "INT_R_X25Y140.WW2BEG1.WL1END1",
+ "INT_R_X25Y144.SS6BEG1.LV9",
+ "INT_R_X27Y136.WW2BEG1.NW6END2",
+ "INT_R_X27Y139.NW2BEG3.WW4END3",
+ "INT_R_X29Y126.WW4BEG2.NN6END2",
+ "INT_R_X29Y128.WW4BEG2.NW6END2",
+ "INT_R_X29Y129.LVB12.NW6END3",
+ "INT_R_X29Y129.SS6BEG1.NW6END2",
+ "INT_R_X29Y130.WW4BEG2.NW6END2",
+ "INT_R_X29Y132.NW6BEG2.NW6END2",
+ "INT_R_X29Y132.WW4BEG2.LVB12",
+ "INT_R_X29Y134.LVB12.NW6END3",
+ "INT_R_X29Y134.WW4BEG2.LVB12",
+ "INT_R_X31Y100.LVB0.LV18",
+ "INT_R_X31Y101.LV0.LV18",
+ "INT_R_X31Y102.LVB0.LV18",
+ "INT_R_X31Y103.LV0.LV18",
+ "INT_R_X31Y112.LV0.LV18",
+ "INT_R_X31Y112.LVB0.LVB12",
+ "INT_R_X31Y113.LVB0.LV18",
+ "INT_R_X31Y114.LVB0.LVB12",
+ "INT_R_X31Y116.LVB0.LV18",
+ "INT_R_X31Y117.LV0.LV18",
+ "INT_R_X31Y119.NN6BEG3.LV18",
+ "INT_R_X31Y121.LV0.LV18",
+ "INT_R_X31Y124.NW6BEG2.LVB12",
+ "INT_R_X31Y125.NW6BEG2.LVB12",
+ "INT_R_X31Y125.NW6BEG3.NN6END3",
+ "INT_R_X31Y126.NW6BEG2.LVB12",
+ "INT_R_X31Y128.NW6BEG2.LVB12",
+ "INT_R_X31Y130.NW6BEG3.LV18",
+ "INT_R_X31Y135.LH0.LV18",
+ "INT_R_X31Y139.WW4BEG3.LV18",
+ "INT_R_X31Y58.LV0.LH12",
+ "INT_R_X31Y59.LV0.LH12",
+ "INT_R_X31Y62.LV0.LH12",
+ "INT_R_X31Y63.LV0.LH12",
+ "INT_R_X31Y64.LV0.LH12",
+ "INT_R_X31Y65.LV0.LH12",
+ "INT_R_X31Y66.LV0.LH12",
+ "INT_R_X31Y67.LV0.LH12",
+ "INT_R_X31Y76.LV0.LV18",
+ "INT_R_X31Y77.LV0.LV18",
+ "INT_R_X31Y80.LV0.LV18",
+ "INT_R_X31Y81.LV0.LV18",
+ "INT_R_X31Y82.LV0.LV18",
+ "INT_R_X31Y83.LV0.LV18",
+ "INT_R_X31Y84.LV0.LV18",
+ "INT_R_X31Y85.LV0.LV18",
+ "INT_R_X31Y94.LV0.LV18",
+ "INT_R_X31Y95.LV0.LV18",
+ "INT_R_X31Y98.LV0.LV18",
+ "INT_R_X31Y99.LV0.LV18",
+ "INT_R_X35Y107.LV18.LV0",
+ "INT_R_X35Y109.SE6BEG0.LV0",
+ "INT_R_X35Y125.LV18.LH0",
+ "INT_R_X35Y127.LV18.LH0",
+ "INT_R_X35Y71.SE6BEG0.LV0",
+ "INT_R_X35Y89.LV18.LV0",
+ "INT_R_X37Y101.LV18.LV0",
+ "INT_R_X37Y103.LV18.LV0",
+ "INT_R_X37Y105.LV18.LV0",
+ "INT_R_X37Y105.SS6BEG0.SE6END0",
+ "INT_R_X37Y115.LV18.LH0",
+ "INT_R_X37Y117.LV18.LH0",
+ "INT_R_X37Y119.LV18.LH0",
+ "INT_R_X37Y121.LV18.LH0",
+ "INT_R_X37Y123.LV18.LH0",
+ "INT_R_X37Y43.SE6BEG0.LV0",
+ "INT_R_X37Y47.SE6BEG0.LV0",
+ "INT_R_X37Y61.LV18.LV0",
+ "INT_R_X37Y63.SE6BEG0.LV0",
+ "INT_R_X37Y65.LV18.LV0",
+ "INT_R_X37Y67.SE6BEG0.SE6END0",
+ "INT_R_X37Y79.LV18.LV0",
+ "INT_R_X37Y81.LV18.LV0",
+ "INT_R_X37Y83.LV18.LV0",
+ "INT_R_X37Y85.SE6BEG0.LV0",
+ "INT_R_X37Y87.SE6BEG0.LV0",
+ "INT_R_X37Y97.LV18.LV0",
+ "INT_R_X37Y99.LV18.LV0",
+ "INT_R_X37Y99.SE6BEG0.SS6END0",
+ "INT_R_X39Y39.EE2BEG0.SE6END0",
+ "INT_R_X39Y43.SE2BEG0.SE6END0",
+ "INT_R_X39Y59.SE6BEG0.SE6END0",
+ "INT_R_X39Y63.SE2BEG0.SE6END0",
+ "INT_R_X39Y77.EE2BEG0.SS6END0",
+ "INT_R_X39Y81.SE2BEG0.SE6END0",
+ "INT_R_X39Y83.SS6BEG0.SE6END0",
+ "INT_R_X39Y95.SE6BEG0.SE6END0",
+ "INT_R_X3Y69.SW6BEG0.SE6END0",
+ "INT_R_X41Y39.ER1BEG1.EE2END0",
+ "INT_R_X41Y49.SE6BEG0.SS6END0",
+ "INT_R_X41Y55.SS6BEG0.SE6END0",
+ "INT_R_X41Y77.ER1BEG1.EE2END0",
+ "INT_R_X41Y91.SE6BEG0.SE6END0",
+ "INT_R_X43Y32.IMUX34.ER1END1",
+ "INT_R_X43Y37.IMUX34.SL1END1",
+ "INT_R_X43Y38.IMUX34.SE2END1",
+ "INT_R_X43Y38.SL1BEG1.SR1END1",
+ "INT_R_X43Y39.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y39.SR1BEG1.SS6END0",
+ "INT_R_X43Y40.LV0.NR1END0",
+ "INT_R_X43Y40.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y41.LV0.NR1END0",
+ "INT_R_X43Y43.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y44.LV0.NR1END0",
+ "INT_R_X43Y44.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y45.LV0.NR1END0",
+ "INT_R_X43Y45.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y45.SS6BEG0.SE6END0",
+ "INT_R_X43Y46.LV0.NR1END0",
+ "INT_R_X43Y46.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y47.LV0.NR1END0",
+ "INT_R_X43Y47.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y48.LV0.NR1END0",
+ "INT_R_X43Y48.NR1BEG0.LOGIC_OUTS18",
+ "INT_R_X43Y49.LV0.NR1END0",
+ "INT_R_X43Y58.LH0.LV18",
+ "INT_R_X43Y59.LH0.LV18",
+ "INT_R_X43Y61.IMUX34.SR1BEG_S0",
+ "INT_R_X43Y61.SR1BEG_S0.WW4END_S0_0",
+ "INT_R_X43Y62.LH0.LV18",
+ "INT_R_X43Y63.LH0.LV18",
+ "INT_R_X43Y64.LH0.LV18",
+ "INT_R_X43Y65.LH0.LV18",
+ "INT_R_X43Y66.LH0.LV18",
+ "INT_R_X43Y67.LH0.LV18",
+ "INT_R_X43Y75.IMUX34.SL1END1",
+ "INT_R_X43Y76.IMUX34.SE2END1",
+ "INT_R_X43Y76.SL1BEG1.ER1END1",
+ "INT_R_X43Y87.ER1BEG1.SE6END0",
+ "INT_R_X43Y87.IMUX34.WR1END1",
+ "LIOB33_SING_X0Y0.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_SING_X0Y0.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_SING_X0Y0.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_SING_X0Y0.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_SING_X0Y0.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y1.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y1.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y11.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y11.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y11.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y11.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y11.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y11.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y11.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y11.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y11.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y11.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y11.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y11.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y111.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y111.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y111.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y111.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y17.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y17.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y17.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y17.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y17.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y17.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y17.IOB_Y1.PULLTYPE.PULLDOWN",
+ "LIOB33_X0Y17.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y19.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y19.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y19.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y19.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y19.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y19.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y19.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y19.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y19.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y19.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y3.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y3.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y3.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y3.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y3.IOB_Y0.SLEW.SLOW",
+ "LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y3.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y3.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y3.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
+ "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y43.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y43.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "LIOB33_X0Y43.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y43.IOB_Y1.SLEW.SLOW",
+ "LIOB33_X0Y5.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y5.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y5.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y5.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y5.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y5.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y5.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y5.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y5.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y5.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y7.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y7.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y7.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y7.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y7.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y7.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y7.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y7.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y7.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y7.IOB_Y1.ZINV_D",
+ "LIOB33_X0Y9.IOB_Y0.IN_ONLY",
+ "LIOB33_X0Y9.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y9.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
+ "LIOB33_X0Y9.IOB_Y0.SLEW.FAST",
+ "LIOB33_X0Y9.IOB_Y0.ZINV_D",
+ "LIOB33_X0Y9.IOB_Y1.IN_ONLY",
+ "LIOB33_X0Y9.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "LIOB33_X0Y9.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
+ "LIOB33_X0Y9.IOB_Y1.SLEW.FAST",
+ "LIOB33_X0Y9.IOB_Y1.ZINV_D",
+ "RIOB33_X43Y25.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y25.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y25.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y25.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y25.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y25.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y25.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y25.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y25.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y31.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y31.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y31.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y31.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y31.IOB_Y0.SLEW.SLOW",
+ "RIOB33_X43Y31.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y31.IOB_Y1.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y31.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y37.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y37.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y37.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y37.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y37.IOB_Y0.SLEW.SLOW",
+ "RIOB33_X43Y37.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y37.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y37.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y37.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y37.IOB_Y1.SLEW.SLOW",
+ "RIOB33_X43Y39.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y39.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y39.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y39.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y39.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y39.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y39.IOB_Y1.IN_ONLY",
+ "RIOB33_X43Y39.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y39.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y39.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y39.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y39.IOB_Y1.ZINV_D",
+ "RIOB33_X43Y43.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y43.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y43.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y43.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y43.IOB_Y1.IN_ONLY",
+ "RIOB33_X43Y43.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y43.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y43.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y43.IOB_Y1.ZINV_D",
+ "RIOB33_X43Y45.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y45.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y45.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y45.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y45.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y45.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y45.IOB_Y1.IN_ONLY",
+ "RIOB33_X43Y45.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y45.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y45.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y45.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y45.IOB_Y1.ZINV_D",
+ "RIOB33_X43Y47.IOB_Y0.IN_ONLY",
+ "RIOB33_X43Y47.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y47.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y47.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y47.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y47.IOB_Y0.ZINV_D",
+ "RIOB33_X43Y47.IOB_Y1.IN_ONLY",
+ "RIOB33_X43Y47.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
+ "RIOB33_X43Y47.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y47.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y47.IOB_Y1.SLEW.FAST",
+ "RIOB33_X43Y47.IOB_Y1.ZINV_D",
+ "RIOB33_X43Y61.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y61.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y61.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y61.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y61.IOB_Y1.SLEW.SLOW",
+ "RIOB33_X43Y75.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y75.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
+ "RIOB33_X43Y75.IOB_Y0.SLEW.SLOW",
+ "RIOB33_X43Y75.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y75.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y75.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y75.IOB_Y1.SLEW.SLOW",
+ "RIOB33_X43Y87.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y87.IOB_Y0.PULLTYPE.PULLDOWN",
+ "RIOB33_X43Y87.IOB_Y0.SLEW.FAST",
+ "RIOB33_X43Y87.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
+ "RIOB33_X43Y87.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
+ "RIOB33_X43Y87.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
+ "RIOB33_X43Y87.IOB_Y1.PULLTYPE.NONE",
+ "RIOB33_X43Y87.IOB_Y1.SLEW.SLOW"
]
}
