Updating the arty-a7 harness based on "Merge pull request #941 from litghost/fixup_arty_harnes". See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/Info.md b/Info.md index 5c99869..c454fe1 100644 --- a/Info.md +++ b/Info.md
@@ -37,7 +37,7 @@ # Details -Last updated on Thu 11 Jul 2019 05:54:48 PM UTC (2019-07-11T17:54:48+00:00). +Last updated on Thu 11 Jul 2019 08:32:50 PM UTC (2019-07-11T20:32:50+00:00). Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [24d852c](https://github.com/SymbiFlow/prjxray/commit/24d852c016e938ca655222ef44219de465b94d6e). @@ -97,16 +97,16 @@ * [`8c6097166bf4b43969c49894dc464d1202f19683d7287a63ec709bc867d97105 ./artix7/element_counts.csv`](./artix7/element_counts.csv) * [`6864d8edcef442cb129f83b9c5cd27be85d1b4bded8007bbeadcfc70717f8c48 ./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt`](./artix7/gridinfo/grid-xc7a50tfgg484-1-db.txt) * [`2b18b3806f0e58024469eac1fe11749d04c6b035d2c2eafa7d2f30bf57173fa9 ./artix7/harness/README.md`](./artix7/harness/README.md) - * [`b270ca64ce9a15a0a2cde99523bab6e7ba748fbca804dd600ccb2c21a4224c85 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit) - * [`134f6438b4dbbd511c823e80548970359e9468b2509e6614732ef2d591613c53 ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp) + * [`189a65a8ccea8f891a6eb11024636c57ef76824629fbc70f08173caa21de05c0 ./artix7/harness/arty-a7/pmod/design.bit`](./artix7/harness/arty-a7/pmod/design.bit) + * [`5cdb00acf930a418c544ef7d18fd41b0a42808284fcf5e4332923c6a012dfa0a ./artix7/harness/arty-a7/pmod/design.dcp`](./artix7/harness/arty-a7/pmod/design.dcp) * [`39236ffb06698077ee3f06edd6d64c0167793cefab4acda71f219a5cf3a20f76 ./artix7/harness/arty-a7/pmod/design.json`](./artix7/harness/arty-a7/pmod/design.json) * [`fb90ad5fe10750f33d5802e1409ebc2406f7b0adab4bf6ef12b53c0e100b43ea ./artix7/harness/arty-a7/pmod/design.txt`](./artix7/harness/arty-a7/pmod/design.txt) - * [`5e4504596aaca26baf85309f7e223a9e45af410971af8c21b375f8151e9e6a53 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit) - * [`6c20fcdb578030f58da1082539828d2785065a598f8ca9c2d14b49d3a6ebe834 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp) - * [`63af3a7ba401751dc4b03cd2db38d5a4c6d20279117307138fee3fcb92ab1119 ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) - * [`7d2429e6bcedecaf6f0db4f2f04860b5b6dc4b036495815a70edc4a036361310 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt) - * [`e492a4c97f0d0a10cd07e0badb0b81f084e2d1a88ba06ab5b705e90ef6003076 ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit) - * [`e2dbcf498c7efe26d6a4ab14733bf3acfe51798bc1d2cd7f4e0e77fc95f40225 ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp) + * [`94a9cd37523ad06463f5eeffcac01bc90078fba44ba2a321bad81ec858b46854 ./artix7/harness/arty-a7/swbut/design.bit`](./artix7/harness/arty-a7/swbut/design.bit) + * [`dfc8063e0ec0c55d47010c0c2b9eab04f0524cda27c1d4e6c4ede63a1d4b9490 ./artix7/harness/arty-a7/swbut/design.dcp`](./artix7/harness/arty-a7/swbut/design.dcp) + * [`944dcf3cdecc2c0d0a88b14d86e8de13c86a3430bbadc711359fa7939a2ab747 ./artix7/harness/arty-a7/swbut/design.json`](./artix7/harness/arty-a7/swbut/design.json) + * [`884af447661ff1cb653cd8280602c2348435366b35bf2627e2221af34899d191 ./artix7/harness/arty-a7/swbut/design.txt`](./artix7/harness/arty-a7/swbut/design.txt) + * [`07957c1776d7cd95382181d955726dbd07e7065364722d905bb671f25d6a3adc ./artix7/harness/arty-a7/uart/design.bit`](./artix7/harness/arty-a7/uart/design.bit) + * [`6f548987f5e1539c8b1ef662b84ad960b628fe20983630fd6db7ca20842ca5fb ./artix7/harness/arty-a7/uart/design.dcp`](./artix7/harness/arty-a7/uart/design.dcp) * [`62586079b9ffd917ff5a5d4edcae802b161a7ed4f6af1c776731dcd10c87d096 ./artix7/harness/arty-a7/uart/design.json`](./artix7/harness/arty-a7/uart/design.json) * [`0583aa7502ee7a0303510c524f5500d8e1b9598aa26016d3d0e4e9623bf8ab8d ./artix7/harness/arty-a7/uart/design.txt`](./artix7/harness/arty-a7/uart/design.txt) * [`4f590875a7851c6d036ab171421b12100f517af74229ad47d8e21fdb6e09b09e ./artix7/harness/basys3/swbut/design.bit`](./artix7/harness/basys3/swbut/design.bit)
diff --git a/artix7/harness/arty-a7/pmod/design.bit b/artix7/harness/arty-a7/pmod/design.bit index f69a3de..2b1a531 100644 --- a/artix7/harness/arty-a7/pmod/design.bit +++ b/artix7/harness/arty-a7/pmod/design.bit Binary files differ
diff --git a/artix7/harness/arty-a7/pmod/design.dcp b/artix7/harness/arty-a7/pmod/design.dcp index 3977d16..1a35df9 100644 --- a/artix7/harness/arty-a7/pmod/design.dcp +++ b/artix7/harness/arty-a7/pmod/design.dcp Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.bit b/artix7/harness/arty-a7/swbut/design.bit index 220c617..c187ad7 100644 --- a/artix7/harness/arty-a7/swbut/design.bit +++ b/artix7/harness/arty-a7/swbut/design.bit Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.dcp b/artix7/harness/arty-a7/swbut/design.dcp index 2180649..21cc5af 100644 --- a/artix7/harness/arty-a7/swbut/design.dcp +++ b/artix7/harness/arty-a7/swbut/design.dcp Binary files differ
diff --git a/artix7/harness/arty-a7/swbut/design.json b/artix7/harness/arty-a7/swbut/design.json index 23f4932..14f632f 100644 --- a/artix7/harness/arty-a7/swbut/design.json +++ b/artix7/harness/arty-a7/swbut/design.json
@@ -14,33 +14,33 @@ }, { "name": "din[0]", - "node": "INT_L_X0Y102/EE2BEG2", + "node": "INT_L_X0Y104/EE2BEG2", "pin": "A8", - "wire": "VBRK_X9Y107/VBRK_EE2A2", + "wire": "VBRK_X9Y109/VBRK_EE2A2", "wires_outside_roi": [ "BRKH_INT_X0Y99/BRKH_INT_LVB_L4", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2", + "BRKH_INT_X0Y99/BRKH_INT_NN6C2", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4", "HCLK_L_X4Y130/HCLK_LV16", - "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2", + "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2", "INT_L_X0Y100/LVB_L4", + "INT_L_X0Y100/NN6D2", "INT_L_X0Y101/LVB_L5", - "INT_L_X0Y102/EE2BEG2", + "INT_L_X0Y101/NN6E2", "INT_L_X0Y102/LVB_L6", - "INT_L_X0Y102/SS6END2", + "INT_L_X0Y102/NN2BEG2", + "INT_L_X0Y102/NN6END2", "INT_L_X0Y103/LVB_L7", - "INT_L_X0Y103/SS6E2", + "INT_L_X0Y103/NN2A2", + "INT_L_X0Y104/EE2BEG2", "INT_L_X0Y104/LVB_L8", - "INT_L_X0Y104/SS6D2", + "INT_L_X0Y104/NN2END2", "INT_L_X0Y105/LVB_L9", - "INT_L_X0Y105/SS6C2", "INT_L_X0Y106/LVB_L10", - "INT_L_X0Y106/SS6B2", "INT_L_X0Y107/LVB_L11", - "INT_L_X0Y107/SS6A2", "INT_L_X0Y108/LVB_L12", "INT_L_X0Y108/LV_L0", - "INT_L_X0Y108/SS6BEG2", "INT_L_X0Y109/LV_L1", "INT_L_X0Y110/LV_L2", "INT_L_X0Y111/LV_L3", @@ -63,10 +63,14 @@ "INT_L_X0Y126/LV_L18", "INT_L_X0Y126/NR1END0", "INT_L_X0Y96/LVB_L0", + "INT_L_X0Y96/NN6BEG2", "INT_L_X0Y97/LVB_L1", + "INT_L_X0Y97/NN6A2", "INT_L_X0Y98/LVB_L2", + "INT_L_X0Y98/NN6B2", "INT_L_X0Y99/LVB_L3", - "INT_R_X1Y102/EE2A2", + "INT_L_X0Y99/NN6C2", + "INT_R_X1Y104/EE2A2", "IO_INT_INTERFACE_L_X0Y125/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y125/INT_INTERFACE_LOGIC_OUTS_L_B18", "LIOB33_X0Y125/IOB_IBUF1", @@ -76,76 +80,48 @@ "LIOI3_X0Y125/LIOI_IBUF1", "LIOI3_X0Y125/LIOI_ILOGIC1_D", "L_TERM_INT_X2Y131/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y107/VBRK_EE2A2" + "VBRK_X9Y109/VBRK_EE2A2" ] }, { "name": "din[1]", - "node": "INT_L_X0Y104/EE2BEG2", + "node": "INT_L_X0Y108/EE2BEG2", "pin": "C11", - "wire": "VBRK_X9Y109/VBRK_EE2A2", + "wire": "VBRK_X9Y113/VBRK_EE2A2", "wires_outside_roi": [ - "BRKH_INT_X0Y99/BRKH_INT_L_LV10", - "BRKH_INT_X0Y99/BRKH_INT_NN6A1", - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4", - "HCLK_L_X4Y130/HCLK_LV17", - "HCLK_L_X4Y130/HCLK_NR1BEG0", - "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2", - "INT_L_X0Y100/LV_L11", - "INT_L_X0Y100/NN6B1", - "INT_L_X0Y101/LV_L12", - "INT_L_X0Y101/NN6C1", - "INT_L_X0Y102/LV_L13", - "INT_L_X0Y102/NN6D1", - "INT_L_X0Y103/LV_L14", - "INT_L_X0Y103/NN6E1", - "INT_L_X0Y104/EE2BEG2", - "INT_L_X0Y104/ER1END2", - "INT_L_X0Y104/LV_L15", - "INT_L_X0Y104/NN6END1", - "INT_L_X0Y104/WR1BEG2", - "INT_L_X0Y105/LV_L16", - "INT_L_X0Y106/LV_L17", - "INT_L_X0Y107/LV_L0", - "INT_L_X0Y107/LV_L18", - "INT_L_X0Y108/LV_L1", - "INT_L_X0Y109/LV_L2", - "INT_L_X0Y110/LV_L3", - "INT_L_X0Y111/LV_L4", - "INT_L_X0Y112/LV_L5", - "INT_L_X0Y113/LV_L6", - "INT_L_X0Y114/LV_L7", - "INT_L_X0Y115/LV_L8", - "INT_L_X0Y116/LV_L9", - "INT_L_X0Y117/LV_L10", - "INT_L_X0Y118/LV_L11", - "INT_L_X0Y119/LV_L12", - "INT_L_X0Y120/LV_L13", - "INT_L_X0Y121/LV_L14", - "INT_L_X0Y122/LV_L15", - "INT_L_X0Y123/LV_L16", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8", + "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2", + "INT_L_X0Y108/EE2BEG2", + "INT_L_X0Y108/SE6END2", + "INT_L_X0Y108/SW6E2", + "INT_L_X0Y109/SW6D2", + "INT_L_X0Y110/SW6C2", + "INT_L_X0Y111/SW6B2", + "INT_L_X0Y112/SW6A2", + "INT_L_X0Y123/EL1BEG3", + "INT_L_X0Y124/EL1BEG_N3", "INT_L_X0Y124/LOGIC_OUTS_L18", - "INT_L_X0Y124/LV_L17", - "INT_L_X0Y124/NR1BEG0", - "INT_L_X0Y125/LV_L18", - "INT_L_X0Y125/NR1END0", - "INT_L_X0Y89/LV_L0", - "INT_L_X0Y90/LV_L1", - "INT_L_X0Y91/LV_L2", - "INT_L_X0Y92/LV_L3", - "INT_L_X0Y93/LV_L4", - "INT_L_X0Y94/LV_L5", - "INT_L_X0Y95/LV_L6", - "INT_L_X0Y96/LV_L7", - "INT_L_X0Y97/LV_L8", - "INT_L_X0Y98/LV_L9", - "INT_L_X0Y98/NN6BEG1", - "INT_L_X0Y99/LV_L10", - "INT_L_X0Y99/NN6A1", - "INT_R_X1Y104/EE2A2", - "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_ER1BEG2", - "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_WR1END2", + "INT_R_X1Y108/EE2A2", + "INT_R_X1Y112/LVB0", + "INT_R_X1Y112/SW6BEG2", + "INT_R_X1Y113/LVB1", + "INT_R_X1Y114/LVB2", + "INT_R_X1Y115/LVB3", + "INT_R_X1Y116/LVB4", + "INT_R_X1Y117/LVB5", + "INT_R_X1Y118/LVB6", + "INT_R_X1Y119/LVB7", + "INT_R_X1Y120/LVB8", + "INT_R_X1Y121/LVB9", + "INT_R_X1Y122/LVB10", + "INT_R_X1Y123/EL1END3", + "INT_R_X1Y123/LVB11", + "INT_R_X1Y123/NR1BEG3", + "INT_R_X1Y124/LVB12", + "INT_R_X1Y124/NR1END3", + "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_SE4C2", + "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_SW4END2", "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_LOGIC_OUTS_L_B18", "LIOB33_X0Y123/IOB_IBUF0", @@ -154,46 +130,47 @@ "LIOI3_X0Y123/LIOI_I0", "LIOI3_X0Y123/LIOI_IBUF0", "LIOI3_X0Y123/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y109/L_TERM_INT_WR1BEG3", + "L_TERM_INT_X2Y113/L_TERM_INT_SW4C2", "L_TERM_INT_X2Y129/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y109/VBRK_EE2A2" + "VBRK_X9Y113/VBRK_EE2A2" ] }, { "name": "din[2]", - "node": "INT_L_X0Y106/EE2BEG2", + "node": "INT_L_X0Y112/EE2BEG2", "pin": "C10", - "wire": "VBRK_X9Y111/VBRK_EE2A2", + "wire": "VBRK_X9Y117/VBRK_EE2A2", "wires_outside_roi": [ - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6", - "INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2", - "INT_L_X0Y106/EE2BEG2", - "INT_L_X0Y106/SS6END2", - "INT_L_X0Y107/SS6E2", - "INT_L_X0Y108/SS6D2", - "INT_L_X0Y109/SS6C2", - "INT_L_X0Y110/SS6B2", - "INT_L_X0Y111/SS6A2", - "INT_L_X0Y112/LVB_L0", - "INT_L_X0Y112/SS6BEG2", - "INT_L_X0Y113/LVB_L1", - "INT_L_X0Y114/LVB_L2", - "INT_L_X0Y115/LVB_L3", - "INT_L_X0Y116/LVB_L4", - "INT_L_X0Y117/LVB_L5", - "INT_L_X0Y118/LVB_L6", - "INT_L_X0Y119/LVB_L7", - "INT_L_X0Y120/LVB_L8", - "INT_L_X0Y121/LVB_L9", - "INT_L_X0Y122/LVB_L10", + "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11", + "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12", + "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2", + "INT_L_X0Y112/EE2BEG2", + "INT_L_X0Y112/EL1END2", + "INT_L_X0Y112/WL1BEG2", + "INT_L_X0Y112/WL1END3", + "INT_L_X0Y113/SE6E0", + "INT_L_X0Y113/WL1END_N1_3", + "INT_L_X0Y114/SE6D0", + "INT_L_X0Y115/SE6C0", + "INT_L_X0Y116/SE6B0", + "INT_L_X0Y117/SE6A0", + "INT_L_X0Y117/SS6END0", + "INT_L_X0Y117/SW6BEG0", + "INT_L_X0Y118/SS6E0", + "INT_L_X0Y119/SS6D0", + "INT_L_X0Y120/SS6C0", + "INT_L_X0Y121/SS6B0", + "INT_L_X0Y122/SS6A0", "INT_L_X0Y123/LOGIC_OUTS_L18", - "INT_L_X0Y123/LVB_L11", - "INT_L_X0Y123/NL1BEG_N3", - "INT_L_X0Y123/NR1BEG3", - "INT_L_X0Y124/LVB_L12", - "INT_L_X0Y124/NR1END3", - "INT_R_X1Y106/EE2A2", + "INT_L_X0Y123/SS6BEG0", + "INT_R_X1Y112/EE2A2", + "INT_R_X1Y112/WL1BEG3", + "INT_R_X1Y113/SE6END0", + "INT_R_X1Y113/WL1BEG_N3", + "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_WL1END2", + "IO_INT_INTERFACE_L_X0Y117/INT_INTERFACE_SE4BEG0", + "IO_INT_INTERFACE_L_X0Y117/INT_INTERFACE_SW4A0", "IO_INT_INTERFACE_L_X0Y123/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y123/INT_INTERFACE_LOGIC_OUTS_L_B18", "LIOB33_X0Y123/IOB_IBUF1", @@ -202,168 +179,92 @@ "LIOI3_X0Y123/LIOI_I1", "LIOI3_X0Y123/LIOI_IBUF1", "LIOI3_X0Y123/LIOI_ILOGIC1_D", + "L_TERM_INT_X2Y117/L_TERM_INT_WL1BEG2", + "L_TERM_INT_X2Y122/L_TERM_INT_SW4BEG0", "L_TERM_INT_X2Y128/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y111/VBRK_EE2A2" + "VBRK_X9Y117/VBRK_EE2A2" ] }, { "name": "din[3]", - "node": "INT_L_X0Y108/EE2BEG2", + "node": "INT_L_X0Y116/EE2BEG2", "pin": "A10", - "wire": "VBRK_X9Y113/VBRK_EE2A2", + "wire": "VBRK_X9Y121/VBRK_EE2A2", "wires_outside_roi": [ - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8", - "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2", - "INT_L_X0Y108/EE2BEG2", - "INT_L_X0Y108/EL1END2", - "INT_L_X0Y108/SL1END3", - "INT_L_X0Y108/WL1BEG2", - "INT_L_X0Y109/EL1END3", - "INT_L_X0Y109/SL1BEG3", - "INT_L_X0Y109/WL1BEG3", - "INT_L_X0Y110/SS6END0", - "INT_L_X0Y110/WL1BEG_N3", - "INT_L_X0Y111/SS6E0", - "INT_L_X0Y112/SS6D0", - "INT_L_X0Y113/SS6C0", - "INT_L_X0Y114/SS6B0", - "INT_L_X0Y115/SS6A0", - "INT_L_X0Y116/SS6BEG0", - "INT_L_X0Y116/SS6END0", - "INT_L_X0Y117/SS6E0", - "INT_L_X0Y118/SS6D0", - "INT_L_X0Y119/SS6C0", - "INT_L_X0Y120/SS6B0", - "INT_L_X0Y121/SS6A0", + "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0", + "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2", + "INT_L_X0Y116/EE2BEG2", + "INT_L_X0Y116/EL1END2", + "INT_L_X0Y116/SE2END3", + "INT_L_X0Y116/SW2A3", + "INT_L_X0Y116/WL1BEG2", + "INT_L_X0Y117/SW2BEG3", + "INT_L_X0Y117/WL1END3", + "INT_L_X0Y118/SE6E0", + "INT_L_X0Y118/WL1END_N1_3", + "INT_L_X0Y119/SE6D0", + "INT_L_X0Y120/SE6C0", + "INT_L_X0Y121/SE6B0", "INT_L_X0Y122/LOGIC_OUTS_L18", - "INT_L_X0Y122/SS6BEG0", - "INT_R_X1Y108/EE2A2", - "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_EL1BEG2", - "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_WL1END2", - "IO_INT_INTERFACE_L_X0Y109/INT_INTERFACE_EL1BEG3", - "IO_INT_INTERFACE_L_X0Y109/INT_INTERFACE_WL1END3", + "INT_L_X0Y122/SE6A0", + "INT_L_X0Y122/SW6BEG0", + "INT_R_X1Y116/EE2A2", + "INT_R_X1Y117/WL1BEG3", + "INT_R_X1Y118/SE6END0", + "INT_R_X1Y118/WL1BEG_N3", + "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_SE2A3", + "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_SW2A3", + "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_WL1END2", "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_LOGIC_OUTS_L_B18", + "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_SE4BEG0", + "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_SW4A0", "LIOB33_X0Y121/IOB_IBUF0", "LIOI3_X0Y121/IOI_ILOGIC0_O", "LIOI3_X0Y121/IOI_LOGIC_OUTS18_1", "LIOI3_X0Y121/LIOI_I0", "LIOI3_X0Y121/LIOI_IBUF0", "LIOI3_X0Y121/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y113/L_TERM_INT_WL1BEG2", - "L_TERM_INT_X2Y114/L_TERM_INT_WR1BEG2", + "L_TERM_INT_X2Y121/L_TERM_INT_SW2BEG3", + "L_TERM_INT_X2Y121/L_TERM_INT_WL1BEG2", + "L_TERM_INT_X2Y127/L_TERM_INT_SW4BEG0", "L_TERM_INT_X2Y127/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y113/VBRK_EE2A2" + "VBRK_X9Y121/VBRK_EE2A2" ] }, { "name": "din[4]", - "node": "INT_L_X0Y110/EE2BEG2", - "pin": "D9", - "wire": "VBRK_X9Y115/VBRK_EE2A2", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9", - "CMT_FIFO_R_X7Y112/CMT_FIFO_WW2A0_9", - "CMT_FIFO_R_X7Y124/CMT_FIFO_SE4C0_3", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_WW2A0_10", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SE4C0_0", - "HCLK_L_X4Y130/HCLK_LV4", - "INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2", - "INT_INTERFACE_R_X1Y110/INT_INTERFACE_WW2A0", - "INT_INTERFACE_R_X1Y116/INT_INTERFACE_SE4C0", - "INT_L_X0Y110/EE2BEG2", - "INT_L_X0Y110/ER1END2", - "INT_L_X0Y110/WR1BEG2", - "INT_L_X0Y110/WW2END0", - "INT_L_X0Y120/LV_L0", - "INT_L_X0Y120/SE6BEG0", - "INT_L_X0Y121/LV_L1", - "INT_L_X0Y122/LV_L2", - "INT_L_X0Y123/LV_L3", - "INT_L_X0Y124/LV_L4", - "INT_L_X0Y125/LV_L5", - "INT_L_X0Y126/LV_L6", - "INT_L_X0Y127/LV_L7", - "INT_L_X0Y128/LV_L8", - "INT_L_X0Y129/LV_L9", - "INT_L_X0Y130/LV_L10", - "INT_L_X0Y131/LV_L11", - "INT_L_X0Y132/LV_L12", - "INT_L_X0Y133/LV_L13", - "INT_L_X0Y134/LV_L14", - "INT_L_X0Y135/LV_L15", - "INT_L_X0Y136/LV_L16", - "INT_L_X0Y137/LOGIC_OUTS_L18", - "INT_L_X0Y137/LV_L17", - "INT_L_X0Y137/NR1BEG0", - "INT_L_X0Y138/LV_L18", - "INT_L_X0Y138/NR1END0", - "INT_R_X1Y110/EE2A2", - "INT_R_X1Y110/WW2A0", - "INT_R_X1Y116/SE6E0", - "INT_R_X1Y117/SE6D0", - "INT_R_X1Y118/SE6C0", - "INT_R_X1Y119/SE6B0", - "INT_R_X1Y120/SE6A0", - "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_ER1BEG2", - "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_WR1END2", - "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L18", - "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L_B18", - "LIOB33_X0Y137/IOB_IBUF1", - "LIOI3_TBYTETERM_X0Y137/IOI_ILOGIC1_O", - "LIOI3_TBYTETERM_X0Y137/IOI_LOGIC_OUTS18_0", - "LIOI3_TBYTETERM_X0Y137/LIOI_I1", - "LIOI3_TBYTETERM_X0Y137/LIOI_IBUF1", - "LIOI3_TBYTETERM_X0Y137/LIOI_ILOGIC1_D", - "L_TERM_INT_X2Y115/L_TERM_INT_WR1BEG3", - "L_TERM_INT_X2Y143/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y115/VBRK_EE2A2", - "VBRK_X9Y115/VBRK_WW2A0", - "VBRK_X9Y121/VBRK_SE4C0" - ] - }, - { - "name": "din[5]", - "node": "INT_L_X0Y112/EE2BEG2", + "node": "INT_L_X0Y120/EE2BEG2", "pin": "C9", - "wire": "VBRK_X9Y117/VBRK_EE2A2", + "wire": "VBRK_X9Y125/VBRK_EE2A2", "wires_outside_roi": [ - "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12", - "HCLK_R_X5Y130/HCLK_LVB9", - "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2", - "INT_L_X0Y112/EE2BEG2", - "INT_L_X0Y112/SE6END2", - "INT_L_X0Y112/SW6E2", - "INT_L_X0Y113/SW6D2", - "INT_L_X0Y114/SW6C2", - "INT_L_X0Y115/SW6B2", - "INT_L_X0Y116/SW6A2", - "INT_L_X0Y127/EL1BEG3", - "INT_L_X0Y128/EL1BEG_N3", + "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_7", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_4", + "HCLK_L_X4Y130/HCLK_SS6D0", + "INT_INTERFACE_R_X1Y120/INT_INTERFACE_EE2A2", + "INT_L_X0Y120/EE2BEG2", + "INT_L_X0Y120/EL1END2", + "INT_L_X0Y120/SL1END3", + "INT_L_X0Y120/WL1BEG2", + "INT_L_X0Y121/EL1END3", + "INT_L_X0Y121/SL1BEG3", + "INT_L_X0Y121/WL1BEG3", + "INT_L_X0Y122/SS6END0", + "INT_L_X0Y122/WL1BEG_N3", + "INT_L_X0Y123/SS6E0", + "INT_L_X0Y124/SS6D0", + "INT_L_X0Y125/SS6C0", + "INT_L_X0Y126/SS6B0", + "INT_L_X0Y127/SS6A0", "INT_L_X0Y128/LOGIC_OUTS_L18", - "INT_R_X1Y112/EE2A2", - "INT_R_X1Y116/LVB0", - "INT_R_X1Y116/SW6BEG2", - "INT_R_X1Y117/LVB1", - "INT_R_X1Y118/LVB2", - "INT_R_X1Y119/LVB3", - "INT_R_X1Y120/LVB4", - "INT_R_X1Y121/LVB5", - "INT_R_X1Y122/LVB6", - "INT_R_X1Y123/LVB7", - "INT_R_X1Y124/LVB8", - "INT_R_X1Y125/LVB9", - "INT_R_X1Y126/LVB10", - "INT_R_X1Y127/EL1END3", - "INT_R_X1Y127/LVB11", - "INT_R_X1Y127/NR1BEG3", - "INT_R_X1Y128/LVB12", - "INT_R_X1Y128/NR1END3", - "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_SE4C2", - "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_SW4END2", + "INT_L_X0Y128/SS6BEG0", + "INT_R_X1Y120/EE2A2", + "IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_WL1END2", + "IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_EL1BEG3", + "IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_WL1END3", "IO_INT_INTERFACE_L_X0Y128/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y128/INT_INTERFACE_LOGIC_OUTS_L_B18", "LIOB33_X0Y127/IOB_IBUF0", @@ -372,62 +273,39 @@ "LIOI3_X0Y127/LIOI_I0", "LIOI3_X0Y127/LIOI_IBUF0", "LIOI3_X0Y127/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y117/L_TERM_INT_SW4C2", + "L_TERM_INT_X2Y125/L_TERM_INT_WL1BEG2", + "L_TERM_INT_X2Y126/L_TERM_INT_WR1BEG2", "L_TERM_INT_X2Y134/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y117/VBRK_EE2A2" + "VBRK_X9Y125/VBRK_EE2A2" ] }, { - "name": "din[6]", - "node": "INT_L_X0Y114/EE2BEG2", + "name": "din[5]", + "node": "INT_L_X0Y124/EE2BEG2", "pin": "B9", - "wire": "VBRK_X9Y119/VBRK_EE2A2", + "wire": "VBRK_X9Y129/VBRK_EE2A2", "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1", - "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14", - "HCLK_L_X4Y130/HCLK_LV14", - "INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2", - "INT_L_X0Y110/LV_L0", - "INT_L_X0Y110/NE6A0", - "INT_L_X0Y110/NW6BEG0", - "INT_L_X0Y111/LV_L1", - "INT_L_X0Y111/NE6B0", - "INT_L_X0Y112/LV_L2", - "INT_L_X0Y112/NE6C0", - "INT_L_X0Y113/LV_L3", - "INT_L_X0Y113/NE6D0", - "INT_L_X0Y114/EE2BEG2", - "INT_L_X0Y114/EL1END2", - "INT_L_X0Y114/LV_L4", - "INT_L_X0Y114/NE6E0", - "INT_L_X0Y114/NW2END_S0_0", - "INT_L_X0Y114/WL1BEG2", - "INT_L_X0Y115/LV_L5", - "INT_L_X0Y115/NW2END0", - "INT_L_X0Y116/LV_L6", - "INT_L_X0Y117/LV_L7", - "INT_L_X0Y118/LV_L8", - "INT_L_X0Y119/LV_L9", - "INT_L_X0Y120/LV_L10", - "INT_L_X0Y121/LV_L11", - "INT_L_X0Y122/LV_L12", - "INT_L_X0Y123/LV_L13", - "INT_L_X0Y124/LV_L14", - "INT_L_X0Y125/LV_L15", - "INT_L_X0Y126/LV_L16", + "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_11", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_8", + "HCLK_L_X4Y130/HCLK_SS2A3", + "HCLK_L_X4Y130/HCLK_SS2END_N0_3", + "INT_INTERFACE_R_X1Y124/INT_INTERFACE_EE2A2", + "INT_L_X0Y124/EE2BEG2", + "INT_L_X0Y124/EL1END2", + "INT_L_X0Y124/SS2END3", + "INT_L_X0Y124/WL1BEG2", + "INT_L_X0Y125/SS2A3", + "INT_L_X0Y125/SS2END_N0_3", + "INT_L_X0Y126/EL1END3", + "INT_L_X0Y126/SS2BEG3", + "INT_L_X0Y126/WL1BEG3", "INT_L_X0Y127/LOGIC_OUTS_L18", - "INT_L_X0Y127/LV_L17", - "INT_L_X0Y127/NR1BEG0", - "INT_L_X0Y128/LV_L18", - "INT_L_X0Y128/NR1END0", - "INT_R_X1Y114/EE2A2", - "INT_R_X1Y114/NE6END0", - "INT_R_X1Y114/NW2BEG0", - "INT_R_X1Y115/NW2A0", - "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_NE4BEG0", - "IO_INT_INTERFACE_L_X0Y110/INT_INTERFACE_NW4A0", - "IO_INT_INTERFACE_L_X0Y114/INT_INTERFACE_EL1BEG2", - "IO_INT_INTERFACE_L_X0Y114/INT_INTERFACE_WL1END2", + "INT_L_X0Y127/WL1BEG_N3", + "INT_R_X1Y124/EE2A2", + "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_WL1END2", + "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_EL1BEG3", + "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_WL1END3", "IO_INT_INTERFACE_L_X0Y127/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y127/INT_INTERFACE_LOGIC_OUTS_L_B18", "LIOB33_X0Y127/IOB_IBUF1", @@ -436,43 +314,29 @@ "LIOI3_X0Y127/LIOI_I1", "LIOI3_X0Y127/LIOI_IBUF1", "LIOI3_X0Y127/LIOI_ILOGIC1_D", - "L_TERM_INT_X2Y115/L_TERM_INT_NW4BEG0", - "L_TERM_INT_X2Y119/L_TERM_INT_WL1BEG2", + "L_TERM_INT_X2Y129/L_TERM_INT_WL1BEG2", + "L_TERM_INT_X2Y132/L_TERM_INT_WR1BEG2", "L_TERM_INT_X2Y133/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y119/VBRK_EE2A2" + "VBRK_X9Y129/VBRK_EE2A2" ] }, { - "name": "din[7]", - "node": "INT_L_X0Y116/EE2BEG2", + "name": "din[6]", + "node": "INT_L_X0Y128/EE2BEG2", "pin": "B8", - "wire": "VBRK_X9Y121/VBRK_EE2A2", + "wire": "VBRK_X9Y134/VBRK_EE2A2", "wires_outside_roi": [ - "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3", - "CMT_FIFO_R_X7Y124/CMT_FIFO_SE4C0_9", - "CMT_FIFO_R_X7Y124/CMT_FIFO_WW2A0_3", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SE4C0_6", - "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_WW2A0_0", - "HCLK_R_X5Y130/HCLK_SE6C0", - "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2", - "INT_INTERFACE_R_X1Y116/INT_INTERFACE_WW2A0", - "INT_INTERFACE_R_X1Y122/INT_INTERFACE_SE4C0", - "INT_L_X0Y116/EE2BEG2", - "INT_L_X0Y116/ER1END2", - "INT_L_X0Y116/WR1BEG2", - "INT_L_X0Y116/WW2END0", + "CMT_FIFO_R_X7Y137/CMT_FIFO_EE2A2_3", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_EE2A2_3", + "INT_INTERFACE_R_X1Y128/INT_INTERFACE_EE2A2", "INT_L_X0Y126/LOGIC_OUTS_L18", - "INT_L_X0Y126/SE6BEG0", - "INT_R_X1Y116/EE2A2", - "INT_R_X1Y116/WW2A0", - "INT_R_X1Y122/SE6E0", - "INT_R_X1Y123/SE6D0", - "INT_R_X1Y124/SE6C0", - "INT_R_X1Y125/SE6B0", - "INT_R_X1Y126/SE6A0", - "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_ER1BEG2", - "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_WR1END2", + "INT_L_X0Y126/NR1BEG0", + "INT_L_X0Y127/NL1BEG2", + "INT_L_X0Y127/NL1BEG_N3", + "INT_L_X0Y127/NR1END0", + "INT_L_X0Y128/EE2BEG2", + "INT_L_X0Y128/NL1END2", + "INT_R_X1Y128/EE2A2", "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_LOGIC_OUTS_L18", "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_LOGIC_OUTS_L_B18", "LIOB33_X0Y125/IOB_IBUF0", @@ -481,17 +345,249 @@ "LIOI3_X0Y125/LIOI_I0", "LIOI3_X0Y125/LIOI_IBUF0", "LIOI3_X0Y125/LIOI_ILOGIC0_D", - "L_TERM_INT_X2Y121/L_TERM_INT_WR1BEG3", "L_TERM_INT_X2Y132/TERM_INT_LOGIC_OUTS_L_B18", - "VBRK_X9Y121/VBRK_EE2A2", - "VBRK_X9Y121/VBRK_WW2A0", - "VBRK_X9Y127/VBRK_SE4C0" + "VBRK_X9Y134/VBRK_EE2A2" + ] + }, + { + "name": "din[7]", + "node": "INT_L_X0Y132/EE2BEG2", + "pin": "D9", + "wire": "VBRK_X9Y138/VBRK_EE2A2", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y137/CMT_FIFO_EE2A2_7", + "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_EE2A2_7", + "INT_INTERFACE_R_X1Y132/INT_INTERFACE_EE2A2", + "INT_L_X0Y132/EE2BEG2", + "INT_L_X0Y132/EL1END2", + "INT_L_X0Y132/WL1BEG2", + "INT_L_X0Y132/WL1END3", + "INT_L_X0Y133/SE6E0", + "INT_L_X0Y133/WL1END_N1_3", + "INT_L_X0Y134/SE6D0", + "INT_L_X0Y135/SE6C0", + "INT_L_X0Y136/SE6B0", + "INT_L_X0Y137/LOGIC_OUTS_L18", + "INT_L_X0Y137/SE6A0", + "INT_L_X0Y137/SW6BEG0", + "INT_R_X1Y132/EE2A2", + "INT_R_X1Y132/WL1BEG3", + "INT_R_X1Y133/SE6END0", + "INT_R_X1Y133/WL1BEG_N3", + "IO_INT_INTERFACE_L_X0Y132/INT_INTERFACE_EL1BEG2", + "IO_INT_INTERFACE_L_X0Y132/INT_INTERFACE_WL1END2", + "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L18", + "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L_B18", + "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_SE4BEG0", + "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_SW4A0", + "LIOB33_X0Y137/IOB_IBUF1", + "LIOI3_TBYTETERM_X0Y137/IOI_ILOGIC1_O", + "LIOI3_TBYTETERM_X0Y137/IOI_LOGIC_OUTS18_0", + "LIOI3_TBYTETERM_X0Y137/LIOI_I1", + "LIOI3_TBYTETERM_X0Y137/LIOI_IBUF1", + "LIOI3_TBYTETERM_X0Y137/LIOI_ILOGIC1_D", + "L_TERM_INT_X2Y138/L_TERM_INT_WL1BEG2", + "L_TERM_INT_X2Y143/L_TERM_INT_SW4BEG0", + "L_TERM_INT_X2Y143/TERM_INT_LOGIC_OUTS_L_B18", + "VBRK_X9Y138/VBRK_EE2A2" ] }, { "name": "dout[0]", - "node": "INT_R_X23Y133/LH12", + "node": "INT_R_X23Y117/LH12", "pin": "H5", + "wire": "VBRK_X61Y122/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y117/CLBLL_LH12", + "CLBLL_L_X26Y117/CLBLL_LH10", + "CLBLL_R_X31Y117/CLBLL_LH6", + "CLBLM_L_X32Y117/CLBLM_LH6", + "CLBLM_L_X36Y117/CLBLM_LH2", + "CLBLM_R_X25Y117/CLBLM_LH10", + "CLBLM_R_X33Y117/CLBLM_LH4", + "CLBLM_R_X35Y117/CLBLM_LH2", + "CLK_FEED_X60Y122/CLK_FEED_LH12", + "DSP_L_X34Y115/DSP_LH4_2", + "INT_INTERFACE_L_X34Y117/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y117/INT_INTERFACE_LH12", + "INT_L_X24Y117/LH11", + "INT_L_X26Y117/LH9", + "INT_L_X30Y117/LH7", + "INT_L_X32Y117/LH5", + "INT_L_X34Y117/LH3", + "INT_L_X36Y117/LH1", + "INT_R_X25Y117/LH10", + "INT_R_X27Y117/LH8", + "INT_R_X31Y117/LH6", + "INT_R_X33Y117/LH4", + "INT_R_X35Y117/LH2", + "INT_R_X37Y117/LH0", + "PCIE_BOT_X71Y115/PCIE_LH8_17", + "PCIE_INT_INTERFACE_L_X30Y117/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y117/INT_INTERFACE_LH8", + "VBRK_X61Y122/VBRK_LH12", + "VBRK_X66Y122/VBRK_LH10", + "VBRK_X80Y122/VBRK_LH6", + "VBRK_X85Y122/VBRK_LH4" + ] + }, + { + "name": "dout[1]", + "node": "INT_R_X23Y121/LH12", + "pin": "J5", + "wire": "VBRK_X61Y126/VBRK_LH12", + "wires_outside_roi": [ + "CLBLL_L_X24Y121/CLBLL_LH12", + "CLBLL_L_X26Y121/CLBLL_LH10", + "CLBLL_R_X31Y121/CLBLL_LH6", + "CLBLM_L_X32Y121/CLBLM_LH6", + "CLBLM_L_X36Y121/CLBLM_LH2", + "CLBLM_R_X25Y121/CLBLM_LH10", + "CLBLM_R_X33Y121/CLBLM_LH4", + "CLBLM_R_X35Y121/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_0", + "DSP_L_X34Y120/DSP_LH4_1", + "INT_INTERFACE_L_X34Y121/INT_INTERFACE_LH4", + "INT_INTERFACE_R_X23Y121/INT_INTERFACE_LH12", + "INT_L_X24Y121/LH11", + "INT_L_X26Y121/LH9", + "INT_L_X30Y121/LH7", + "INT_L_X32Y121/LH5", + "INT_L_X34Y121/LH3", + "INT_L_X36Y121/LH1", + "INT_R_X25Y121/LH10", + "INT_R_X27Y121/LH8", + "INT_R_X31Y121/LH6", + "INT_R_X33Y121/LH4", + "INT_R_X35Y121/LH2", + "INT_R_X37Y121/LH0", + "PCIE_INT_INTERFACE_L_X30Y121/INT_INTERFACE_LH8", + "PCIE_INT_INTERFACE_R_X27Y121/INT_INTERFACE_LH8", + "PCIE_TOP_X71Y125/PCIE_LH8_1", + "VBRK_X61Y126/VBRK_LH12", + "VBRK_X66Y126/VBRK_LH10", + "VBRK_X80Y126/VBRK_LH6", + "VBRK_X85Y126/VBRK_LH4" + ] + }, + { + "name": "dout[2]", + "node": "INT_L_X2Y117/SW6BEG0", + "pin": "T9", + "wire": "VBRK_X9Y122/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_4", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_1", + "INT_INTERFACE_R_X1Y117/INT_INTERFACE_SW4A0", + "INT_L_X0Y113/SW6END0", + "INT_R_X1Y113/SW6E0", + "INT_R_X1Y114/SW6D0", + "INT_R_X1Y115/SW6C0", + "INT_R_X1Y116/SW6B0", + "INT_R_X1Y117/SW6A0", + "VBRK_X9Y122/VBRK_SW4A0" + ] + }, + { + "name": "dout[3]", + "node": "INT_L_X2Y121/SW6BEG0", + "pin": "T10", + "wire": "VBRK_X9Y126/VBRK_SW4A0", + "wires_outside_roi": [ + "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_8", + "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_5", + "INT_INTERFACE_R_X1Y121/INT_INTERFACE_SW4A0", + "INT_L_X0Y117/SW6END0", + "INT_R_X1Y117/SW6E0", + "INT_R_X1Y118/SW6D0", + "INT_R_X1Y119/SW6C0", + "INT_R_X1Y120/SW6B0", + "INT_R_X1Y121/SW6A0", + "VBRK_X9Y126/VBRK_SW4A0" + ] + }, + { + "name": "dout[4]", + "node": "INT_R_X23Y125/LH12", + "pin": "F6", + "wire": "VBRK_X61Y131/VBRK_LH12", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y125/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_LH6_0", + "CLBLL_L_X24Y125/CLBLL_LH12", + "CLBLL_L_X26Y125/CLBLL_LH10", + "CLBLL_L_X28Y125/CLBLL_LH8", + "CLBLL_R_X31Y125/CLBLL_LH4", + "CLBLM_L_X32Y125/CLBLM_LH4", + "CLBLM_R_X25Y125/CLBLM_LH10", + "CLBLM_R_X27Y125/CLBLM_LH8", + "CLBLM_R_X29Y125/CLBLM_LH6", + "CLBLM_R_X33Y125/CLBLM_LH2", + "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_4", + "DSP_L_X34Y125/DSP_LH2_0", + "INT_INTERFACE_L_X34Y125/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y125/INT_INTERFACE_LH12", + "INT_L_X24Y125/LH11", + "INT_L_X26Y125/LH9", + "INT_L_X28Y125/LH7", + "INT_L_X30Y125/LH5", + "INT_L_X32Y125/LH3", + "INT_L_X34Y125/LH1", + "INT_R_X25Y125/LH10", + "INT_R_X27Y125/LH8", + "INT_R_X29Y125/LH6", + "INT_R_X31Y125/LH4", + "INT_R_X33Y125/LH2", + "INT_R_X35Y125/LH0", + "VBRK_X61Y131/VBRK_LH12", + "VBRK_X66Y131/VBRK_LH10", + "VBRK_X80Y131/VBRK_LH4", + "VBRK_X85Y131/VBRK_LH2" + ] + }, + { + "name": "dout[5]", + "node": "INT_R_X23Y129/LH12", + "pin": "J4", + "wire": "VBRK_X61Y135/VBRK_LH12", + "wires_outside_roi": [ + "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_LH6", + "BRAM_L_X30Y125/BRAM_LH6_4", + "CLBLL_L_X24Y129/CLBLL_LH12", + "CLBLL_L_X26Y129/CLBLL_LH10", + "CLBLL_L_X28Y129/CLBLL_LH8", + "CLBLL_R_X31Y129/CLBLL_LH4", + "CLBLM_L_X32Y129/CLBLM_LH4", + "CLBLM_R_X25Y129/CLBLM_LH10", + "CLBLM_R_X27Y129/CLBLM_LH8", + "CLBLM_R_X29Y129/CLBLM_LH6", + "CLBLM_R_X33Y129/CLBLM_LH2", + "CLK_FEED_X60Y135/CLK_FEED_LH12", + "DSP_L_X34Y125/DSP_LH2_4", + "INT_INTERFACE_L_X34Y129/INT_INTERFACE_LH2", + "INT_INTERFACE_R_X23Y129/INT_INTERFACE_LH12", + "INT_L_X24Y129/LH11", + "INT_L_X26Y129/LH9", + "INT_L_X28Y129/LH7", + "INT_L_X30Y129/LH5", + "INT_L_X32Y129/LH3", + "INT_L_X34Y129/LH1", + "INT_R_X25Y129/LH10", + "INT_R_X27Y129/LH8", + "INT_R_X29Y129/LH6", + "INT_R_X31Y129/LH4", + "INT_R_X33Y129/LH2", + "INT_R_X35Y129/LH0", + "VBRK_X61Y135/VBRK_LH12", + "VBRK_X66Y135/VBRK_LH10", + "VBRK_X80Y135/VBRK_LH4", + "VBRK_X85Y135/VBRK_LH2" + ] + }, + { + "name": "dout[6]", + "node": "INT_R_X23Y133/LH12", + "pin": "J2", "wire": "VBRK_X61Y139/VBRK_LH12", "wires_outside_roi": [ "BRAM_INT_INTERFACE_L_X30Y133/INT_INTERFACE_LH6", @@ -528,84 +624,9 @@ ] }, { - "name": "dout[1]", - "node": "INT_R_X23Y135/LH12", - "pin": "J5", - "wire": "VBRK_X61Y141/VBRK_LH12", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y135/INT_INTERFACE_LH6", - "BRAM_L_X30Y135/BRAM_LH6_0", - "CLBLL_L_X24Y135/CLBLL_LH12", - "CLBLL_L_X26Y135/CLBLL_LH10", - "CLBLL_L_X28Y135/CLBLL_LH8", - "CLBLL_R_X31Y135/CLBLL_LH4", - "CLBLM_L_X32Y135/CLBLM_LH4", - "CLBLM_R_X25Y135/CLBLM_LH10", - "CLBLM_R_X27Y135/CLBLM_LH8", - "CLBLM_R_X29Y135/CLBLM_LH6", - "CLBLM_R_X33Y135/CLBLM_LH2", - "CLK_FEED_X60Y141/CLK_FEED_LH12", - "DSP_L_X34Y135/DSP_LH2_0", - "INT_INTERFACE_L_X34Y135/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y135/INT_INTERFACE_LH12", - "INT_L_X24Y135/LH11", - "INT_L_X26Y135/LH9", - "INT_L_X28Y135/LH7", - "INT_L_X30Y135/LH5", - "INT_L_X32Y135/LH3", - "INT_L_X34Y135/LH1", - "INT_R_X25Y135/LH10", - "INT_R_X27Y135/LH8", - "INT_R_X29Y135/LH6", - "INT_R_X31Y135/LH4", - "INT_R_X33Y135/LH2", - "INT_R_X35Y135/LH0", - "VBRK_X61Y141/VBRK_LH12", - "VBRK_X66Y141/VBRK_LH10", - "VBRK_X80Y141/VBRK_LH4", - "VBRK_X85Y141/VBRK_LH2" - ] - }, - { - "name": "dout[2]", - "node": "INT_L_X2Y133/SW6BEG0", - "pin": "T9", - "wire": "VBRK_X9Y139/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_8", - "INT_INTERFACE_R_X1Y133/INT_INTERFACE_SW4A0", - "INT_L_X0Y129/SW6END0", - "INT_R_X1Y129/SW6E0", - "INT_R_X1Y130/SW6D0", - "INT_R_X1Y131/SW6C0", - "INT_R_X1Y132/SW6B0", - "INT_R_X1Y133/SW6A0", - "VBRK_X9Y139/VBRK_SW4A0" - ] - }, - { - "name": "dout[3]", - "node": "INT_L_X2Y135/SW6BEG0", - "pin": "T10", - "wire": "VBRK_X9Y141/VBRK_SW4A0", - "wires_outside_roi": [ - "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_10", - "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_10", - "INT_INTERFACE_R_X1Y135/INT_INTERFACE_SW4A0", - "INT_L_X0Y131/SW6END0", - "INT_R_X1Y131/SW6E0", - "INT_R_X1Y132/SW6D0", - "INT_R_X1Y133/SW6C0", - "INT_R_X1Y134/SW6B0", - "INT_R_X1Y135/SW6A0", - "VBRK_X9Y141/VBRK_SW4A0" - ] - }, - { - "name": "dout[4]", + "name": "dout[7]", "node": "INT_R_X23Y137/LH12", - "pin": "F6", + "pin": "H6", "wire": "VBRK_X61Y143/VBRK_LH12", "wires_outside_roi": [ "BRAM_INT_INTERFACE_L_X30Y137/INT_INTERFACE_LH6", @@ -640,123 +661,6 @@ "VBRK_X80Y143/VBRK_LH4", "VBRK_X85Y143/VBRK_LH2" ] - }, - { - "name": "dout[5]", - "node": "INT_R_X23Y139/LH12", - "pin": "J4", - "wire": "VBRK_X61Y145/VBRK_LH12", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y139/INT_INTERFACE_LH6", - "BRAM_L_X30Y135/BRAM_LH6_4", - "CLBLL_L_X24Y139/CLBLL_LH12", - "CLBLL_L_X26Y139/CLBLL_LH10", - "CLBLL_L_X28Y139/CLBLL_LH8", - "CLBLL_R_X31Y139/CLBLL_LH4", - "CLBLM_L_X32Y139/CLBLM_LH4", - "CLBLM_R_X25Y139/CLBLM_LH10", - "CLBLM_R_X27Y139/CLBLM_LH8", - "CLBLM_R_X29Y139/CLBLM_LH6", - "CLBLM_R_X33Y139/CLBLM_LH2", - "CLK_FEED_X60Y145/CLK_FEED_LH12", - "DSP_L_X34Y135/DSP_LH2_4", - "INT_INTERFACE_L_X34Y139/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y139/INT_INTERFACE_LH12", - "INT_L_X24Y139/LH11", - "INT_L_X26Y139/LH9", - "INT_L_X28Y139/LH7", - "INT_L_X30Y139/LH5", - "INT_L_X32Y139/LH3", - "INT_L_X34Y139/LH1", - "INT_R_X25Y139/LH10", - "INT_R_X27Y139/LH8", - "INT_R_X29Y139/LH6", - "INT_R_X31Y139/LH4", - "INT_R_X33Y139/LH2", - "INT_R_X35Y139/LH0", - "VBRK_X61Y145/VBRK_LH12", - "VBRK_X66Y145/VBRK_LH10", - "VBRK_X80Y145/VBRK_LH4", - "VBRK_X85Y145/VBRK_LH2" - ] - }, - { - "name": "dout[6]", - "node": "INT_R_X23Y141/LH12", - "pin": "J2", - "wire": "VBRK_X61Y147/VBRK_LH12", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y141/INT_INTERFACE_LH6", - "BRAM_L_X30Y140/BRAM_LH6_1", - "CLBLL_L_X24Y141/CLBLL_LH12", - "CLBLL_L_X26Y141/CLBLL_LH10", - "CLBLL_L_X28Y141/CLBLL_LH8", - "CLBLL_R_X31Y141/CLBLL_LH4", - "CLBLM_L_X32Y141/CLBLM_LH4", - "CLBLM_R_X25Y141/CLBLM_LH10", - "CLBLM_R_X27Y141/CLBLM_LH8", - "CLBLM_R_X29Y141/CLBLM_LH6", - "CLBLM_R_X33Y141/CLBLM_LH2", - "CLK_FEED_X60Y147/CLK_FEED_LH12", - "DSP_L_X34Y140/DSP_LH2_1", - "INT_INTERFACE_L_X34Y141/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y141/INT_INTERFACE_LH12", - "INT_L_X24Y141/LH11", - "INT_L_X26Y141/LH9", - "INT_L_X28Y141/LH7", - "INT_L_X30Y141/LH5", - "INT_L_X32Y141/LH3", - "INT_L_X34Y141/LH1", - "INT_R_X25Y141/LH10", - "INT_R_X27Y141/LH8", - "INT_R_X29Y141/LH6", - "INT_R_X31Y141/LH4", - "INT_R_X33Y141/LH2", - "INT_R_X35Y141/LH0", - "VBRK_X61Y147/VBRK_LH12", - "VBRK_X66Y147/VBRK_LH10", - "VBRK_X80Y147/VBRK_LH4", - "VBRK_X85Y147/VBRK_LH2" - ] - }, - { - "name": "dout[7]", - "node": "INT_R_X23Y143/LH12", - "pin": "H6", - "wire": "VBRK_X61Y149/VBRK_LH12", - "wires_outside_roi": [ - "BRAM_INT_INTERFACE_L_X30Y143/INT_INTERFACE_LH6", - "BRAM_L_X30Y140/BRAM_LH6_3", - "CLBLL_L_X24Y143/CLBLL_LH12", - "CLBLL_L_X26Y143/CLBLL_LH10", - "CLBLL_L_X28Y143/CLBLL_LH8", - "CLBLL_R_X31Y143/CLBLL_LH4", - "CLBLM_L_X32Y143/CLBLM_LH4", - "CLBLM_R_X25Y143/CLBLM_LH10", - "CLBLM_R_X27Y143/CLBLM_LH8", - "CLBLM_R_X29Y143/CLBLM_LH6", - "CLBLM_R_X33Y143/CLBLM_LH2", - "CLK_FEED_X60Y149/CLK_FEED_LH12", - "DSP_L_X34Y140/DSP_LH2_3", - "INT_INTERFACE_L_X34Y143/INT_INTERFACE_LH2", - "INT_INTERFACE_R_X23Y143/INT_INTERFACE_LH12", - "INT_L_X24Y143/LH11", - "INT_L_X26Y143/LH9", - "INT_L_X28Y143/LH7", - "INT_L_X30Y143/LH5", - "INT_L_X32Y143/LH3", - "INT_L_X34Y143/LH1", - "INT_R_X25Y143/LH10", - "INT_R_X27Y143/LH8", - "INT_R_X29Y143/LH6", - "INT_R_X31Y143/LH4", - "INT_R_X33Y143/LH2", - "INT_R_X35Y143/LH0", - "VBRK_X61Y149/VBRK_LH12", - "VBRK_X66Y149/VBRK_LH10", - "VBRK_X80Y149/VBRK_LH4", - "VBRK_X85Y149/VBRK_LH2" - ] } ], "required_features": [ @@ -819,133 +723,127 @@ "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE", "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0", "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE", - "INT_L_X0Y1.IMUX_L34.WW2END0", - "INT_L_X0Y102.EE2BEG2.SS6END2", - "INT_L_X0Y104.EE2BEG2.ER1END2", - "INT_L_X0Y104.WR1BEG2.NN6END1", - "INT_L_X0Y106.EE2BEG2.SS6END2", - "INT_L_X0Y107.LV_L18.LV_L0", - "INT_L_X0Y108.EE2BEG2.EL1END2", + "INT_L_X0Y1.IMUX_L34.SL1END1", + "INT_L_X0Y102.NN2BEG2.NN6END2", + "INT_L_X0Y104.EE2BEG2.NN2END2", + "INT_L_X0Y108.EE2BEG2.SE6END2", "INT_L_X0Y108.LVB_L12.LV_L0", - "INT_L_X0Y108.SS6BEG2.LVB_L12", - "INT_L_X0Y108.WL1BEG2.SL1END3", - "INT_L_X0Y109.SL1BEG3.EL1END3", - "INT_L_X0Y11.SE6BEG0.SS6END0", - "INT_L_X0Y110.EE2BEG2.ER1END2", - "INT_L_X0Y110.NW6BEG0.LV_L0", - "INT_L_X0Y110.WL1BEG_N3.SS6END0", - "INT_L_X0Y110.WR1BEG2.WW2END0", - "INT_L_X0Y111.LV_L18.LV_L0", - "INT_L_X0Y112.EE2BEG2.SE6END2", - "INT_L_X0Y112.SS6BEG2.LVB_L0", - "INT_L_X0Y113.LV_L18.LV_L0", - "INT_L_X0Y114.EE2BEG2.EL1END2", - "INT_L_X0Y114.WL1BEG2.NW2END_S0_0", - "INT_L_X0Y116.EE2BEG2.ER1END2", - "INT_L_X0Y116.SS6BEG0.SS6END0", - "INT_L_X0Y116.WR1BEG2.WW2END0", - "INT_L_X0Y120.SE6BEG0.LV_L0", - "INT_L_X0Y122.SS6BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y123.NL1BEG_N3.LOGIC_OUTS_L18", - "INT_L_X0Y123.NR1BEG3.NL1BEG_N3", - "INT_L_X0Y124.LVB_L12.NR1END3", - "INT_L_X0Y124.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y125.LV_L18.NR1END0", + "INT_L_X0Y11.SS6BEG0.SS6END0", + "INT_L_X0Y112.EE2BEG2.EL1END2", + "INT_L_X0Y112.WL1BEG2.WL1END3", + "INT_L_X0Y113.LV_L18.SW6END0", + "INT_L_X0Y116.EE2BEG2.EL1END2", + "INT_L_X0Y116.EE2BEG3.SE2END3", + "INT_L_X0Y116.WL1BEG2.SE2END3", + "INT_L_X0Y117.LV_L18.SW6END0", + "INT_L_X0Y117.SW2BEG3.WL1END3", + "INT_L_X0Y117.SW6BEG0.SS6END0", + "INT_L_X0Y120.EE2BEG2.EL1END2", + "INT_L_X0Y120.WL1BEG2.SL1END3", + "INT_L_X0Y121.SL1BEG3.EL1END3", + "INT_L_X0Y122.SW6BEG0.LOGIC_OUTS_L18", + "INT_L_X0Y122.WL1BEG_N3.SS6END0", + "INT_L_X0Y123.SS6BEG0.LOGIC_OUTS_L18", + "INT_L_X0Y124.EE2BEG2.EL1END2", + "INT_L_X0Y124.EE2BEG3.SS2END3", + "INT_L_X0Y124.EL1BEG_N3.LOGIC_OUTS_L18", + "INT_L_X0Y124.WL1BEG2.SS2END3", "INT_L_X0Y125.NR1BEG0.LOGIC_OUTS_L18", "INT_L_X0Y126.LV_L18.NR1END0", - "INT_L_X0Y126.SE6BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y127.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y128.EL1BEG_N3.LOGIC_OUTS_L18", - "INT_L_X0Y128.LV_L18.NR1END0", - "INT_L_X0Y129.LV_L18.SW6END0", - "INT_L_X0Y131.LV_L18.SW6END0", - "INT_L_X0Y137.NR1BEG0.LOGIC_OUTS_L18", - "INT_L_X0Y138.LV_L18.NR1END0", - "INT_L_X0Y15.SS6BEG0.SS6END0", + "INT_L_X0Y126.NR1BEG0.LOGIC_OUTS_L18", + "INT_L_X0Y126.SS2BEG3.EL1END3", + "INT_L_X0Y127.NL1BEG2.NL1BEG_N3", + "INT_L_X0Y127.NL1BEG_N3.NR1END0", + "INT_L_X0Y127.WL1BEG_N3.LOGIC_OUTS_L18", + "INT_L_X0Y128.EE2BEG2.NL1END2", + "INT_L_X0Y128.SS6BEG0.LOGIC_OUTS_L18", + "INT_L_X0Y132.EE2BEG2.EL1END2", + "INT_L_X0Y132.WL1BEG2.WL1END3", + "INT_L_X0Y137.SW6BEG0.LOGIC_OUTS_L18", "INT_L_X0Y17.SS6BEG0.SS6END0", - "INT_L_X0Y2.FAN_ALT1.EL1END3", - "INT_L_X0Y2.IMUX_L34.FAN_BOUNCE1", - "INT_L_X0Y21.SS6BEG0.LV_L0", + "INT_L_X0Y2.IMUX_L34.SS2END1", + "INT_L_X0Y2.SL1BEG1.SR1END1", "INT_L_X0Y23.SS6BEG0.LV_L0", - "INT_L_X0Y3.WL1BEG_N3.SS6END0", - "INT_L_X0Y39.LV_L18.LV_L0", + "INT_L_X0Y27.LV_L18.LV_L0", + "INT_L_X0Y3.SR1BEG1.SS6END0", + "INT_L_X0Y4.SS2BEG1.SR1END1", "INT_L_X0Y41.LV_L18.LV_L0", - "INT_L_X0Y57.LV_L18.LV_L0", + "INT_L_X0Y45.LV_L18.LV_L0", + "INT_L_X0Y5.SR1BEG1.SS6END0", "INT_L_X0Y59.LV_L18.LV_L0", - "INT_L_X0Y75.LV_L18.LV_L0", + "INT_L_X0Y63.LV_L18.LV_L0", "INT_L_X0Y77.LV_L18.LV_L0", - "INT_L_X0Y9.SS6BEG0.SS6END0", - "INT_L_X0Y93.LV_L18.LV_L0", + "INT_L_X0Y81.LV_L18.LV_L0", + "INT_L_X0Y9.SS6BEG0.LV_L0", "INT_L_X0Y95.LV_L18.LV_L0", - "INT_L_X0Y98.NN6BEG1.LV_L9", - "INT_L_X2Y1.WW2BEG0.SS6END0", - "INT_L_X2Y7.SS6BEG0.SE6END0", - "INT_L_X40Y52.EE4BEG0.SE2END0", - "INT_L_X40Y60.SE6BEG0.SE2END0", + "INT_L_X0Y96.NN6BEG2.LVB_L0", + "INT_L_X0Y99.LV_L18.LV_L0", + "INT_L_X38Y66.SE6BEG0.SE2END0", + "INT_L_X40Y62.EE4BEG0.SE6END0", "INT_L_X42Y51.SE2BEG1.ER1END1", - "INT_L_X42Y56.ER1BEG1.SE6END0", - "INT_L_X42Y59.SE2BEG1.ER1END1", - "INT_R_X1Y114.NW2BEG0.NE6END0", - "INT_R_X1Y116.SW6BEG2.LVB0", - "INT_R_X1Y127.NR1BEG3.EL1END3", - "INT_R_X1Y128.LVB12.NR1END3", + "INT_L_X42Y53.SE2BEG1.ER1END1", + "INT_R_X1Y112.SW6BEG2.LVB0", + "INT_R_X1Y113.EL1BEG_N3.SE6END0", + "INT_R_X1Y113.WL1BEG_N3.SE6END0", + "INT_R_X1Y118.WL1BEG_N3.SE6END0", + "INT_R_X1Y123.NR1BEG3.EL1END3", + "INT_R_X1Y124.LVB12.NR1END3", + "INT_R_X1Y133.EL1BEG_N3.SE6END0", + "INT_R_X1Y133.WL1BEG_N3.SE6END0", "INT_R_X35Y101.LV18.LV0", - "INT_R_X35Y103.LV18.LV0", - "INT_R_X35Y105.LV18.LV0", "INT_R_X35Y107.LV18.LV0", + "INT_R_X35Y111.LV18.LV0", "INT_R_X35Y115.LV18.LV0", - "INT_R_X35Y117.LV18.LV0", "INT_R_X35Y119.LV18.LV0", - "INT_R_X35Y121.LV18.LV0", - "INT_R_X35Y123.LV18.LV0", - "INT_R_X35Y125.LV18.LV0", + "INT_R_X35Y125.LV18.LH0", + "INT_R_X35Y129.LV18.LH0", "INT_R_X35Y133.LV18.LH0", - "INT_R_X35Y135.LV18.LH0", "INT_R_X35Y137.LV18.LH0", - "INT_R_X35Y139.LV18.LH0", - "INT_R_X35Y141.LV18.LH0", - "INT_R_X35Y143.LV18.LH0", - "INT_R_X35Y53.EE4BEG0.LV0", - "INT_R_X35Y61.SE6BEG0.LV0", - "INT_R_X35Y63.SE6BEG0.LV0", - "INT_R_X35Y67.SE6BEG0.LV0", - "INT_R_X35Y69.SE6BEG0.LV0", - "INT_R_X35Y71.LV18.LV0", - "INT_R_X35Y79.LV18.LV0", - "INT_R_X35Y81.LV18.LV0", - "INT_R_X35Y83.EE4BEG0.LV0", - "INT_R_X35Y85.LV18.LV0", - "INT_R_X35Y87.LV18.LV0", + "INT_R_X35Y65.SE6BEG0.LV0", + "INT_R_X35Y71.SE6BEG0.LV0", + "INT_R_X35Y75.SE6BEG0.LV0", + "INT_R_X35Y79.SE6BEG0.LV0", + "INT_R_X35Y83.LV18.LV0", "INT_R_X35Y89.LV18.LV0", + "INT_R_X35Y93.LV18.LV0", "INT_R_X35Y97.LV18.LV0", - "INT_R_X35Y99.LV18.LV0", - "INT_R_X37Y57.SE6BEG0.SE6END0", - "INT_R_X37Y59.SE6BEG0.SE6END0", - "INT_R_X37Y63.SE6BEG0.SE6END0", - "INT_R_X37Y65.SE6BEG0.SE6END0", - "INT_R_X39Y53.EE4BEG0.EE4END0", - "INT_R_X39Y53.SE2BEG0.SE6END0", - "INT_R_X39Y55.SE6BEG0.SE6END0", - "INT_R_X39Y59.EE2BEG0.SE6END0", - "INT_R_X39Y61.SE2BEG0.SE6END0", - "INT_R_X39Y83.SE6BEG0.EE4END0", - "INT_R_X41Y51.ER1BEG1.SE6END0", - "INT_R_X41Y59.ER1BEG1.EE2END0", - "INT_R_X41Y73.SE6BEG0.SS6END0", - "INT_R_X41Y79.SS6BEG0.SE6END0", + "INT_R_X37Y103.LV18.LV0", + "INT_R_X37Y117.LV18.LH0", + "INT_R_X37Y121.LV18.LH0", + "INT_R_X37Y61.SE6BEG0.SE6END0", + "INT_R_X37Y63.SE6BEG0.LV0", + "INT_R_X37Y67.SE2BEG0.SE6END0", + "INT_R_X37Y67.SE6BEG0.LV0", + "INT_R_X37Y71.SE6BEG0.SE6END0", + "INT_R_X37Y75.SE6BEG0.SE6END0", + "INT_R_X37Y81.LV18.LV0", + "INT_R_X37Y85.LV18.LV0", + "INT_R_X37Y99.LV18.LV0", + "INT_R_X39Y51.EE2BEG0.SS6END0", + "INT_R_X39Y57.SE6BEG0.SE6END0", + "INT_R_X39Y57.SS6BEG0.SS6END0", + "INT_R_X39Y59.SE6BEG0.SE6END0", + "INT_R_X39Y63.SS6BEG0.SE6END0", + "INT_R_X39Y67.SE6BEG0.SE6END0", + "INT_R_X39Y71.SE6BEG0.SE6END0", + "INT_R_X41Y51.ER1BEG1.EE2END0", + "INT_R_X41Y53.ER1BEG1.SE6END0", + "INT_R_X41Y55.SE6BEG0.SE6END0", + "INT_R_X41Y63.SE6BEG0.SE6END0", + "INT_R_X41Y67.SE6BEG0.SE6END0", "INT_R_X43Y50.IMUX34.SE2END1", - "INT_R_X43Y51.IMUX34.SR1BEG_S0", - "INT_R_X43Y51.SR1BEG_S0.WW4END_S0_0", - "INT_R_X43Y52.IMUX34.SR1BEG_S0", - "INT_R_X43Y52.SR1BEG_S0.WL1END3", - "INT_R_X43Y53.EL1BEG_N3.EE4END0", + "INT_R_X43Y51.ER1BEG1.SE6END0", + "INT_R_X43Y51.IMUX34.WR1END1", + "INT_R_X43Y52.IMUX34.SE2END1", "INT_R_X43Y55.IMUX34.SL1END1", - "INT_R_X43Y56.SL1BEG1.ER1END1", - "INT_R_X43Y58.IMUX34.SE2END1", - "INT_R_X43Y61.IMUX34.SL1END1", - "INT_R_X43Y62.SL1BEG1.SR1END1", - "INT_R_X43Y63.SR1BEG1.SS6END0", - "INT_R_X43Y69.SS6BEG0.SE6END0", + "INT_R_X43Y56.SL1BEG1.SR1END1", + "INT_R_X43Y57.SR1BEG1.SS6END0", + "INT_R_X43Y58.IMUX34.SR1BEG_S0", + "INT_R_X43Y58.SR1BEG_S0.WL1END3", + "INT_R_X43Y59.EL1BEG_N3.SE6END0", + "INT_R_X43Y61.IMUX34.SR1BEG_S0", + "INT_R_X43Y61.SR1BEG_S0.WW4END_S0_0", + "INT_R_X43Y63.SS6BEG0.SE6END0", "LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16", "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE", "LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
diff --git a/artix7/harness/arty-a7/swbut/design.txt b/artix7/harness/arty-a7/swbut/design.txt index 5cfb2dd..32a4fc2 100644 --- a/artix7/harness/arty-a7/swbut/design.txt +++ b/artix7/harness/arty-a7/swbut/design.txt
@@ -1,18 +1,18 @@ name node pin wire clk CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0 E3 HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0 -din[0] INT_L_X0Y102/EE2BEG2 A8 VBRK_X9Y107/VBRK_EE2A2 -din[1] INT_L_X0Y104/EE2BEG2 C11 VBRK_X9Y109/VBRK_EE2A2 -din[2] INT_L_X0Y106/EE2BEG2 C10 VBRK_X9Y111/VBRK_EE2A2 -din[3] INT_L_X0Y108/EE2BEG2 A10 VBRK_X9Y113/VBRK_EE2A2 -din[4] INT_L_X0Y110/EE2BEG2 D9 VBRK_X9Y115/VBRK_EE2A2 -din[5] INT_L_X0Y112/EE2BEG2 C9 VBRK_X9Y117/VBRK_EE2A2 -din[6] INT_L_X0Y114/EE2BEG2 B9 VBRK_X9Y119/VBRK_EE2A2 -din[7] INT_L_X0Y116/EE2BEG2 B8 VBRK_X9Y121/VBRK_EE2A2 -dout[0] INT_R_X23Y133/LH12 H5 VBRK_X61Y139/VBRK_LH12 -dout[1] INT_R_X23Y135/LH12 J5 VBRK_X61Y141/VBRK_LH12 -dout[2] INT_L_X2Y133/SW6BEG0 T9 VBRK_X9Y139/VBRK_SW4A0 -dout[3] INT_L_X2Y135/SW6BEG0 T10 VBRK_X9Y141/VBRK_SW4A0 -dout[4] INT_R_X23Y137/LH12 F6 VBRK_X61Y143/VBRK_LH12 -dout[5] INT_R_X23Y139/LH12 J4 VBRK_X61Y145/VBRK_LH12 -dout[6] INT_R_X23Y141/LH12 J2 VBRK_X61Y147/VBRK_LH12 -dout[7] INT_R_X23Y143/LH12 H6 VBRK_X61Y149/VBRK_LH12 +din[0] INT_L_X0Y104/EE2BEG2 A8 VBRK_X9Y109/VBRK_EE2A2 +din[1] INT_L_X0Y108/EE2BEG2 C11 VBRK_X9Y113/VBRK_EE2A2 +din[2] INT_L_X0Y112/EE2BEG2 C10 VBRK_X9Y117/VBRK_EE2A2 +din[3] INT_L_X0Y116/EE2BEG2 A10 VBRK_X9Y121/VBRK_EE2A2 +din[4] INT_L_X0Y120/EE2BEG2 C9 VBRK_X9Y125/VBRK_EE2A2 +din[5] INT_L_X0Y124/EE2BEG2 B9 VBRK_X9Y129/VBRK_EE2A2 +din[6] INT_L_X0Y128/EE2BEG2 B8 VBRK_X9Y134/VBRK_EE2A2 +din[7] INT_L_X0Y132/EE2BEG2 D9 VBRK_X9Y138/VBRK_EE2A2 +dout[0] INT_R_X23Y117/LH12 H5 VBRK_X61Y122/VBRK_LH12 +dout[1] INT_R_X23Y121/LH12 J5 VBRK_X61Y126/VBRK_LH12 +dout[2] INT_L_X2Y117/SW6BEG0 T9 VBRK_X9Y122/VBRK_SW4A0 +dout[3] INT_L_X2Y121/SW6BEG0 T10 VBRK_X9Y126/VBRK_SW4A0 +dout[4] INT_R_X23Y125/LH12 F6 VBRK_X61Y131/VBRK_LH12 +dout[5] INT_R_X23Y129/LH12 J4 VBRK_X61Y135/VBRK_LH12 +dout[6] INT_R_X23Y133/LH12 J2 VBRK_X61Y139/VBRK_LH12 +dout[7] INT_R_X23Y137/LH12 H6 VBRK_X61Y143/VBRK_LH12
diff --git a/artix7/harness/arty-a7/uart/design.bit b/artix7/harness/arty-a7/uart/design.bit index 9d9416f..a7182fe 100644 --- a/artix7/harness/arty-a7/uart/design.bit +++ b/artix7/harness/arty-a7/uart/design.bit Binary files differ
diff --git a/artix7/harness/arty-a7/uart/design.dcp b/artix7/harness/arty-a7/uart/design.dcp index 821fb1c..0236696 100644 --- a/artix7/harness/arty-a7/uart/design.dcp +++ b/artix7/harness/arty-a7/uart/design.dcp Binary files differ