{
    "info": {
        "GRID_X_MAX": 58,
        "GRID_X_MIN": 10,
        "GRID_Y_MAX": 51,
        "GRID_Y_MIN": 0
    },
    "ports": [
        {
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "G13",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_L_X0Y102/EE2BEG2",
            "pin": "E15",
            "wire": "VBRK_X9Y107/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV15",
                "BRKH_INT_X0Y99/BRKH_INT_NN6C2",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2",
                "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LV_L16",
                "INT_L_X0Y100/NN6D2",
                "INT_L_X0Y101/LV_L17",
                "INT_L_X0Y101/NN6E2",
                "INT_L_X0Y102/EE2BEG2",
                "INT_L_X0Y102/LV_L18",
                "INT_L_X0Y102/NN6END2",
                "INT_L_X0Y78/LOGIC_OUTS_L18",
                "INT_L_X0Y78/NN6BEG0",
                "INT_L_X0Y79/NN6A0",
                "INT_L_X0Y80/NN6B0",
                "INT_L_X0Y81/NN6C0",
                "INT_L_X0Y82/NN6D0",
                "INT_L_X0Y83/NN6E0",
                "INT_L_X0Y83/NN6END_S1_0",
                "INT_L_X0Y84/LVB_L0",
                "INT_L_X0Y84/LV_L0",
                "INT_L_X0Y84/NN6END0",
                "INT_L_X0Y85/LVB_L1",
                "INT_L_X0Y85/LV_L1",
                "INT_L_X0Y86/LVB_L2",
                "INT_L_X0Y86/LV_L2",
                "INT_L_X0Y87/LVB_L3",
                "INT_L_X0Y87/LV_L3",
                "INT_L_X0Y88/LVB_L4",
                "INT_L_X0Y88/LV_L4",
                "INT_L_X0Y89/LVB_L5",
                "INT_L_X0Y89/LV_L5",
                "INT_L_X0Y90/LVB_L6",
                "INT_L_X0Y90/LV_L6",
                "INT_L_X0Y91/LVB_L7",
                "INT_L_X0Y91/LV_L7",
                "INT_L_X0Y92/LVB_L8",
                "INT_L_X0Y92/LV_L8",
                "INT_L_X0Y93/LVB_L9",
                "INT_L_X0Y93/LV_L9",
                "INT_L_X0Y94/LVB_L10",
                "INT_L_X0Y94/LV_L10",
                "INT_L_X0Y95/LVB_L11",
                "INT_L_X0Y95/LV_L11",
                "INT_L_X0Y96/LVB_L12",
                "INT_L_X0Y96/LV_L12",
                "INT_L_X0Y96/NN6BEG2",
                "INT_L_X0Y97/LV_L13",
                "INT_L_X0Y97/NN6A2",
                "INT_L_X0Y98/LV_L14",
                "INT_L_X0Y98/NN6B2",
                "INT_L_X0Y99/LV_L15",
                "INT_L_X0Y99/NN6C2",
                "INT_R_X1Y102/EE2A2",
                "IO_INT_INTERFACE_L_X0Y78/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y78/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y77/IOB_IBUF0",
                "LIOI3_X0Y77/IOI_ILOGIC0_O",
                "LIOI3_X0Y77/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y77/LIOI_I0",
                "LIOI3_X0Y77/LIOI_IBUF0",
                "LIOI3_X0Y77/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y82/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y107/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[1]",
            "node": "INT_L_X0Y104/EE2BEG2",
            "pin": "E16",
            "wire": "VBRK_X9Y109/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV16",
                "BRKH_INT_X0Y99/BRKH_INT_NN6A1",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4",
                "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LV_L17",
                "INT_L_X0Y100/NN6B1",
                "INT_L_X0Y101/LV_L18",
                "INT_L_X0Y101/NN6C1",
                "INT_L_X0Y102/NN6D1",
                "INT_L_X0Y103/NN6E1",
                "INT_L_X0Y104/EE2BEG2",
                "INT_L_X0Y104/ER1END2",
                "INT_L_X0Y104/NN6END1",
                "INT_L_X0Y104/WR1BEG2",
                "INT_L_X0Y77/LOGIC_OUTS_L18",
                "INT_L_X0Y77/NN6BEG0",
                "INT_L_X0Y78/NN6A0",
                "INT_L_X0Y79/NN6B0",
                "INT_L_X0Y80/NN6C0",
                "INT_L_X0Y81/NN6D0",
                "INT_L_X0Y82/NN6E0",
                "INT_L_X0Y82/NN6END_S1_0",
                "INT_L_X0Y83/LV_L0",
                "INT_L_X0Y83/NN6END0",
                "INT_L_X0Y84/LV_L1",
                "INT_L_X0Y85/LV_L2",
                "INT_L_X0Y86/LV_L3",
                "INT_L_X0Y87/LV_L4",
                "INT_L_X0Y88/LV_L5",
                "INT_L_X0Y89/LV_L6",
                "INT_L_X0Y90/LV_L7",
                "INT_L_X0Y91/LV_L8",
                "INT_L_X0Y92/LV_L9",
                "INT_L_X0Y92/NN6BEG1",
                "INT_L_X0Y93/LV_L10",
                "INT_L_X0Y93/NN6A1",
                "INT_L_X0Y94/LV_L11",
                "INT_L_X0Y94/NN6B1",
                "INT_L_X0Y95/LV_L12",
                "INT_L_X0Y95/NN6C1",
                "INT_L_X0Y96/LV_L13",
                "INT_L_X0Y96/NN6D1",
                "INT_L_X0Y97/LV_L14",
                "INT_L_X0Y97/NN6E1",
                "INT_L_X0Y98/LV_L15",
                "INT_L_X0Y98/NN6BEG1",
                "INT_L_X0Y98/NN6END1",
                "INT_L_X0Y99/LV_L16",
                "INT_L_X0Y99/NN6A1",
                "INT_R_X1Y104/EE2A2",
                "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_ER1BEG2",
                "IO_INT_INTERFACE_L_X0Y104/INT_INTERFACE_WR1END2",
                "IO_INT_INTERFACE_L_X0Y77/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y77/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y77/IOB_IBUF1",
                "LIOI3_X0Y77/IOI_ILOGIC1_O",
                "LIOI3_X0Y77/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y77/LIOI_I1",
                "LIOI3_X0Y77/LIOI_IBUF1",
                "LIOI3_X0Y77/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y109/L_TERM_INT_WR1BEG3",
                "L_TERM_INT_X2Y81/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y109/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[2]",
            "node": "INT_L_X0Y106/EE2BEG2",
            "pin": "D15",
            "wire": "VBRK_X9Y111/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV17",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_5",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_6",
                "INT_INTERFACE_R_X1Y106/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LVB_L0",
                "INT_L_X0Y100/LV_L18",
                "INT_L_X0Y101/LVB_L1",
                "INT_L_X0Y102/LVB_L2",
                "INT_L_X0Y103/LVB_L3",
                "INT_L_X0Y104/LVB_L4",
                "INT_L_X0Y105/LVB_L5",
                "INT_L_X0Y106/EE2BEG2",
                "INT_L_X0Y106/LVB_L6",
                "INT_L_X0Y106/SS6END2",
                "INT_L_X0Y107/LVB_L7",
                "INT_L_X0Y107/SS6E2",
                "INT_L_X0Y108/LVB_L8",
                "INT_L_X0Y108/SS6D2",
                "INT_L_X0Y109/LVB_L9",
                "INT_L_X0Y109/SS6C2",
                "INT_L_X0Y110/LVB_L10",
                "INT_L_X0Y110/SS6B2",
                "INT_L_X0Y111/LVB_L11",
                "INT_L_X0Y111/SS6A2",
                "INT_L_X0Y112/LVB_L12",
                "INT_L_X0Y112/SS6BEG2",
                "INT_L_X0Y76/LOGIC_OUTS_L18",
                "INT_L_X0Y76/NN6BEG0",
                "INT_L_X0Y77/NN6A0",
                "INT_L_X0Y78/NN6B0",
                "INT_L_X0Y79/NN6C0",
                "INT_L_X0Y80/NN6D0",
                "INT_L_X0Y81/NN6E0",
                "INT_L_X0Y81/NN6END_S1_0",
                "INT_L_X0Y82/LV_L0",
                "INT_L_X0Y82/NN6END0",
                "INT_L_X0Y83/LV_L1",
                "INT_L_X0Y84/LV_L2",
                "INT_L_X0Y85/LV_L3",
                "INT_L_X0Y86/LV_L4",
                "INT_L_X0Y87/LV_L5",
                "INT_L_X0Y88/LV_L6",
                "INT_L_X0Y89/LV_L7",
                "INT_L_X0Y90/LV_L8",
                "INT_L_X0Y91/LV_L9",
                "INT_L_X0Y92/LV_L10",
                "INT_L_X0Y93/LV_L11",
                "INT_L_X0Y94/LV_L12",
                "INT_L_X0Y95/LV_L13",
                "INT_L_X0Y96/LV_L14",
                "INT_L_X0Y97/LV_L15",
                "INT_L_X0Y98/LV_L16",
                "INT_L_X0Y99/LV_L17",
                "INT_R_X1Y106/EE2A2",
                "IO_INT_INTERFACE_L_X0Y76/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y76/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y75/IOB_IBUF0",
                "LIOI3_X0Y75/IOI_ILOGIC0_O",
                "LIOI3_X0Y75/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y75/LIOI_I0",
                "LIOI3_X0Y75/LIOI_IBUF0",
                "LIOI3_X0Y75/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y80/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y111/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[3]",
            "node": "INT_L_X0Y108/EE2BEG2",
            "pin": "C15",
            "wire": "VBRK_X9Y113/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_NN6BEG3",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8",
                "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/NN6A3",
                "INT_L_X0Y101/NN6B3",
                "INT_L_X0Y102/NN6C3",
                "INT_L_X0Y103/NN6D3",
                "INT_L_X0Y104/NN6E3",
                "INT_L_X0Y105/NN2BEG3",
                "INT_L_X0Y105/NN6END3",
                "INT_L_X0Y106/NN2A3",
                "INT_L_X0Y107/NL1BEG2",
                "INT_L_X0Y107/NN2END3",
                "INT_L_X0Y108/EE2BEG2",
                "INT_L_X0Y108/NL1END2",
                "INT_L_X0Y75/LOGIC_OUTS_L18",
                "INT_L_X0Y75/NN6BEG0",
                "INT_L_X0Y76/NN6A0",
                "INT_L_X0Y77/NN6B0",
                "INT_L_X0Y78/NN6C0",
                "INT_L_X0Y79/NN6D0",
                "INT_L_X0Y80/NN6E0",
                "INT_L_X0Y80/NN6END_S1_0",
                "INT_L_X0Y81/LV_L0",
                "INT_L_X0Y81/NN6END0",
                "INT_L_X0Y82/LV_L1",
                "INT_L_X0Y83/LV_L2",
                "INT_L_X0Y84/LV_L3",
                "INT_L_X0Y85/LV_L4",
                "INT_L_X0Y86/LV_L5",
                "INT_L_X0Y87/LV_L6",
                "INT_L_X0Y88/LV_L7",
                "INT_L_X0Y89/LV_L8",
                "INT_L_X0Y90/LV_L9",
                "INT_L_X0Y91/LV_L10",
                "INT_L_X0Y92/LV_L11",
                "INT_L_X0Y93/LV_L12",
                "INT_L_X0Y94/LV_L13",
                "INT_L_X0Y95/LV_L14",
                "INT_L_X0Y96/LV_L15",
                "INT_L_X0Y97/LV_L16",
                "INT_L_X0Y98/LV_L17",
                "INT_L_X0Y99/LV_L18",
                "INT_L_X0Y99/NN6BEG3",
                "INT_R_X1Y108/EE2A2",
                "IO_INT_INTERFACE_L_X0Y75/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y75/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y75/IOB_IBUF1",
                "LIOI3_X0Y75/IOI_ILOGIC1_O",
                "LIOI3_X0Y75/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y75/LIOI_I1",
                "LIOI3_X0Y75/LIOI_IBUF1",
                "LIOI3_X0Y75/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y79/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y113/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[4]",
            "node": "INT_L_X0Y110/EE2BEG2",
            "pin": "J17",
            "wire": "VBRK_X9Y115/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_LVB_L9",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_9",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_10",
                "HCLK_L_X4Y78/HCLK_LV1",
                "INT_INTERFACE_R_X1Y110/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LVB_L9",
                "INT_L_X0Y101/LVB_L10",
                "INT_L_X0Y102/LVB_L11",
                "INT_L_X0Y103/LVB_L12",
                "INT_L_X0Y103/NN6BEG2",
                "INT_L_X0Y104/NN6A2",
                "INT_L_X0Y105/NN6B2",
                "INT_L_X0Y106/NN6C2",
                "INT_L_X0Y107/NN6D2",
                "INT_L_X0Y108/NN6E2",
                "INT_L_X0Y109/NN6END2",
                "INT_L_X0Y109/NR1BEG2",
                "INT_L_X0Y110/EE2BEG2",
                "INT_L_X0Y110/NR1END2",
                "INT_L_X0Y54/LOGIC_OUTS_L18",
                "INT_L_X0Y54/NR1BEG0",
                "INT_L_X0Y55/LV_L0",
                "INT_L_X0Y55/NR1END0",
                "INT_L_X0Y56/LV_L1",
                "INT_L_X0Y57/LV_L2",
                "INT_L_X0Y58/LV_L3",
                "INT_L_X0Y59/LV_L4",
                "INT_L_X0Y60/LV_L5",
                "INT_L_X0Y61/LV_L6",
                "INT_L_X0Y62/LV_L7",
                "INT_L_X0Y63/LV_L8",
                "INT_L_X0Y64/LV_L9",
                "INT_L_X0Y65/LV_L10",
                "INT_L_X0Y66/LV_L11",
                "INT_L_X0Y67/LV_L12",
                "INT_L_X0Y68/LV_L13",
                "INT_L_X0Y69/LV_L14",
                "INT_L_X0Y70/LV_L15",
                "INT_L_X0Y71/LV_L16",
                "INT_L_X0Y72/LV_L17",
                "INT_L_X0Y73/LV_L0",
                "INT_L_X0Y73/LV_L18",
                "INT_L_X0Y74/LV_L1",
                "INT_L_X0Y75/LV_L2",
                "INT_L_X0Y76/LV_L3",
                "INT_L_X0Y77/LV_L4",
                "INT_L_X0Y78/LV_L5",
                "INT_L_X0Y79/LV_L6",
                "INT_L_X0Y80/LV_L7",
                "INT_L_X0Y81/LV_L8",
                "INT_L_X0Y82/LV_L9",
                "INT_L_X0Y83/LV_L10",
                "INT_L_X0Y84/LV_L11",
                "INT_L_X0Y85/LV_L12",
                "INT_L_X0Y86/LV_L13",
                "INT_L_X0Y87/LV_L14",
                "INT_L_X0Y88/LV_L15",
                "INT_L_X0Y89/LV_L16",
                "INT_L_X0Y90/LV_L17",
                "INT_L_X0Y91/LVB_L0",
                "INT_L_X0Y91/LV_L18",
                "INT_L_X0Y92/LVB_L1",
                "INT_L_X0Y93/LVB_L2",
                "INT_L_X0Y94/LVB_L3",
                "INT_L_X0Y95/LVB_L4",
                "INT_L_X0Y96/LVB_L5",
                "INT_L_X0Y97/LVB_L6",
                "INT_L_X0Y98/LVB_L7",
                "INT_L_X0Y99/LVB_L8",
                "INT_R_X1Y110/EE2A2",
                "IO_INT_INTERFACE_L_X0Y54/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y54/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y53/IOB_IBUF0",
                "LIOI3_X0Y53/IOI_ILOGIC0_O",
                "LIOI3_X0Y53/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y53/LIOI_I0",
                "LIOI3_X0Y53/LIOI_IBUF0",
                "LIOI3_X0Y53/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y57/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y115/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[5]",
            "node": "INT_L_X0Y112/EE2BEG2",
            "pin": "J18",
            "wire": "VBRK_X9Y117/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV9",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12",
                "HCLK_L_X4Y78/HCLK_LV2",
                "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LV_L10",
                "INT_L_X0Y101/LV_L11",
                "INT_L_X0Y102/LV_L12",
                "INT_L_X0Y103/LV_L13",
                "INT_L_X0Y104/LV_L14",
                "INT_L_X0Y105/LV_L15",
                "INT_L_X0Y106/LV_L16",
                "INT_L_X0Y107/LV_L17",
                "INT_L_X0Y108/LV_L18",
                "INT_L_X0Y108/NE6A3",
                "INT_L_X0Y108/NW6BEG3",
                "INT_L_X0Y109/NE6B3",
                "INT_L_X0Y110/NE6C3",
                "INT_L_X0Y111/NE6D3",
                "INT_L_X0Y112/EE2BEG2",
                "INT_L_X0Y112/EL1END2",
                "INT_L_X0Y112/NE6E3",
                "INT_L_X0Y112/WL1BEG2",
                "INT_L_X0Y112/WR1END_S1_0",
                "INT_L_X0Y113/WR1END0",
                "INT_L_X0Y53/LOGIC_OUTS_L18",
                "INT_L_X0Y53/NR1BEG0",
                "INT_L_X0Y54/LV_L0",
                "INT_L_X0Y54/NR1END0",
                "INT_L_X0Y55/LV_L1",
                "INT_L_X0Y56/LV_L2",
                "INT_L_X0Y57/LV_L3",
                "INT_L_X0Y58/LV_L4",
                "INT_L_X0Y59/LV_L5",
                "INT_L_X0Y60/LV_L6",
                "INT_L_X0Y61/LV_L7",
                "INT_L_X0Y62/LV_L8",
                "INT_L_X0Y63/LV_L9",
                "INT_L_X0Y64/LV_L10",
                "INT_L_X0Y65/LV_L11",
                "INT_L_X0Y66/LV_L12",
                "INT_L_X0Y67/LV_L13",
                "INT_L_X0Y68/LV_L14",
                "INT_L_X0Y69/LV_L15",
                "INT_L_X0Y70/LV_L16",
                "INT_L_X0Y71/LV_L17",
                "INT_L_X0Y72/LV_L0",
                "INT_L_X0Y72/LV_L18",
                "INT_L_X0Y73/LV_L1",
                "INT_L_X0Y74/LV_L2",
                "INT_L_X0Y75/LV_L3",
                "INT_L_X0Y76/LV_L4",
                "INT_L_X0Y77/LV_L5",
                "INT_L_X0Y78/LV_L6",
                "INT_L_X0Y79/LV_L7",
                "INT_L_X0Y80/LV_L8",
                "INT_L_X0Y81/LV_L9",
                "INT_L_X0Y82/LV_L10",
                "INT_L_X0Y83/LV_L11",
                "INT_L_X0Y84/LV_L12",
                "INT_L_X0Y85/LV_L13",
                "INT_L_X0Y86/LV_L14",
                "INT_L_X0Y87/LV_L15",
                "INT_L_X0Y88/LV_L16",
                "INT_L_X0Y89/LV_L17",
                "INT_L_X0Y90/LV_L0",
                "INT_L_X0Y90/LV_L18",
                "INT_L_X0Y91/LV_L1",
                "INT_L_X0Y92/LV_L2",
                "INT_L_X0Y93/LV_L3",
                "INT_L_X0Y94/LV_L4",
                "INT_L_X0Y95/LV_L5",
                "INT_L_X0Y96/LV_L6",
                "INT_L_X0Y97/LV_L7",
                "INT_L_X0Y98/LV_L8",
                "INT_L_X0Y99/LV_L9",
                "INT_R_X1Y112/EE2A2",
                "INT_R_X1Y112/NE6END3",
                "INT_R_X1Y112/WR1BEG_S0",
                "INT_R_X1Y113/WR1BEG0",
                "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_NE4BEG3",
                "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_NW4A3",
                "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_EL1BEG2",
                "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_WL1END2",
                "IO_INT_INTERFACE_L_X0Y53/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y53/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y53/IOB_IBUF1",
                "LIOI3_X0Y53/IOI_ILOGIC1_O",
                "LIOI3_X0Y53/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y53/LIOI_I1",
                "LIOI3_X0Y53/LIOI_IBUF1",
                "LIOI3_X0Y53/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y113/L_TERM_INT_NW4BEG3",
                "L_TERM_INT_X2Y117/L_TERM_INT_WL1BEG2",
                "L_TERM_INT_X2Y56/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y117/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[6]",
            "node": "INT_L_X0Y114/EE2BEG2",
            "pin": "K15",
            "wire": "VBRK_X9Y119/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV10",
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_1",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_14",
                "HCLK_L_X4Y78/HCLK_LV3",
                "INT_INTERFACE_R_X1Y114/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LV_L11",
                "INT_L_X0Y101/LV_L12",
                "INT_L_X0Y102/LV_L13",
                "INT_L_X0Y103/LV_L14",
                "INT_L_X0Y104/LV_L15",
                "INT_L_X0Y105/LV_L16",
                "INT_L_X0Y106/LV_L17",
                "INT_L_X0Y107/LV_L18",
                "INT_L_X0Y107/NN6BEG3",
                "INT_L_X0Y108/NN6A3",
                "INT_L_X0Y109/NN6B3",
                "INT_L_X0Y110/NN6C3",
                "INT_L_X0Y111/NN6D3",
                "INT_L_X0Y112/NN6E3",
                "INT_L_X0Y113/NL1BEG2",
                "INT_L_X0Y113/NN6END3",
                "INT_L_X0Y114/EE2BEG2",
                "INT_L_X0Y114/NL1END2",
                "INT_L_X0Y52/LOGIC_OUTS_L18",
                "INT_L_X0Y52/NR1BEG0",
                "INT_L_X0Y53/LV_L0",
                "INT_L_X0Y53/NR1END0",
                "INT_L_X0Y54/LV_L1",
                "INT_L_X0Y55/LV_L2",
                "INT_L_X0Y56/LV_L3",
                "INT_L_X0Y57/LV_L4",
                "INT_L_X0Y58/LV_L5",
                "INT_L_X0Y59/LV_L6",
                "INT_L_X0Y60/LV_L7",
                "INT_L_X0Y61/LV_L8",
                "INT_L_X0Y62/LV_L9",
                "INT_L_X0Y63/LV_L10",
                "INT_L_X0Y64/LV_L11",
                "INT_L_X0Y65/LV_L12",
                "INT_L_X0Y66/LV_L13",
                "INT_L_X0Y67/LV_L14",
                "INT_L_X0Y68/LV_L15",
                "INT_L_X0Y69/LV_L16",
                "INT_L_X0Y70/LV_L17",
                "INT_L_X0Y71/LV_L0",
                "INT_L_X0Y71/LV_L18",
                "INT_L_X0Y72/LV_L1",
                "INT_L_X0Y73/LV_L2",
                "INT_L_X0Y74/LV_L3",
                "INT_L_X0Y75/LV_L4",
                "INT_L_X0Y76/LV_L5",
                "INT_L_X0Y77/LV_L6",
                "INT_L_X0Y78/LV_L7",
                "INT_L_X0Y79/LV_L8",
                "INT_L_X0Y80/LV_L9",
                "INT_L_X0Y81/LV_L10",
                "INT_L_X0Y82/LV_L11",
                "INT_L_X0Y83/LV_L12",
                "INT_L_X0Y84/LV_L13",
                "INT_L_X0Y85/LV_L14",
                "INT_L_X0Y86/LV_L15",
                "INT_L_X0Y87/LV_L16",
                "INT_L_X0Y88/LV_L17",
                "INT_L_X0Y89/LV_L0",
                "INT_L_X0Y89/LV_L18",
                "INT_L_X0Y90/LV_L1",
                "INT_L_X0Y91/LV_L2",
                "INT_L_X0Y92/LV_L3",
                "INT_L_X0Y93/LV_L4",
                "INT_L_X0Y94/LV_L5",
                "INT_L_X0Y95/LV_L6",
                "INT_L_X0Y96/LV_L7",
                "INT_L_X0Y97/LV_L8",
                "INT_L_X0Y98/LV_L9",
                "INT_L_X0Y99/LV_L10",
                "INT_R_X1Y114/EE2A2",
                "IO_INT_INTERFACE_L_X0Y52/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y52/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y51/IOB_IBUF0",
                "LIOI3_X0Y51/IOI_ILOGIC0_O",
                "LIOI3_X0Y51/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y51/LIOI_I0",
                "LIOI3_X0Y51/LIOI_IBUF0",
                "LIOI3_X0Y51/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y55/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y119/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[7]",
            "node": "INT_L_X0Y116/EE2BEG2",
            "pin": "J15",
            "wire": "VBRK_X9Y121/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_L_LV11",
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3",
                "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0",
                "HCLK_L_X4Y78/HCLK_LV4",
                "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LV_L12",
                "INT_L_X0Y101/LV_L13",
                "INT_L_X0Y102/LV_L14",
                "INT_L_X0Y103/LV_L15",
                "INT_L_X0Y104/LV_L16",
                "INT_L_X0Y105/LV_L17",
                "INT_L_X0Y106/LV_L18",
                "INT_L_X0Y106/NE6A3",
                "INT_L_X0Y106/NW6BEG3",
                "INT_L_X0Y107/NE6B3",
                "INT_L_X0Y108/NE6C3",
                "INT_L_X0Y109/NE6D3",
                "INT_L_X0Y110/NE6E3",
                "INT_L_X0Y116/EE2BEG2",
                "INT_L_X0Y116/EE2END2",
                "INT_L_X0Y116/WW2A2",
                "INT_L_X0Y51/LOGIC_OUTS_L18",
                "INT_L_X0Y51/NR1BEG0",
                "INT_L_X0Y52/LV_L0",
                "INT_L_X0Y52/NR1END0",
                "INT_L_X0Y53/LV_L1",
                "INT_L_X0Y54/LV_L2",
                "INT_L_X0Y55/LV_L3",
                "INT_L_X0Y56/LV_L4",
                "INT_L_X0Y57/LV_L5",
                "INT_L_X0Y58/LV_L6",
                "INT_L_X0Y59/LV_L7",
                "INT_L_X0Y60/LV_L8",
                "INT_L_X0Y61/LV_L9",
                "INT_L_X0Y62/LV_L10",
                "INT_L_X0Y63/LV_L11",
                "INT_L_X0Y64/LV_L12",
                "INT_L_X0Y65/LV_L13",
                "INT_L_X0Y66/LV_L14",
                "INT_L_X0Y67/LV_L15",
                "INT_L_X0Y68/LV_L16",
                "INT_L_X0Y69/LV_L17",
                "INT_L_X0Y70/LV_L0",
                "INT_L_X0Y70/LV_L18",
                "INT_L_X0Y71/LV_L1",
                "INT_L_X0Y72/LV_L2",
                "INT_L_X0Y73/LV_L3",
                "INT_L_X0Y74/LV_L4",
                "INT_L_X0Y75/LV_L5",
                "INT_L_X0Y76/LV_L6",
                "INT_L_X0Y77/LV_L7",
                "INT_L_X0Y78/LV_L8",
                "INT_L_X0Y79/LV_L9",
                "INT_L_X0Y80/LV_L10",
                "INT_L_X0Y81/LV_L11",
                "INT_L_X0Y82/LV_L12",
                "INT_L_X0Y83/LV_L13",
                "INT_L_X0Y84/LV_L14",
                "INT_L_X0Y85/LV_L15",
                "INT_L_X0Y86/LV_L16",
                "INT_L_X0Y87/LV_L17",
                "INT_L_X0Y88/LV_L0",
                "INT_L_X0Y88/LV_L18",
                "INT_L_X0Y89/LV_L1",
                "INT_L_X0Y90/LV_L2",
                "INT_L_X0Y91/LV_L3",
                "INT_L_X0Y92/LV_L4",
                "INT_L_X0Y93/LV_L5",
                "INT_L_X0Y94/LV_L6",
                "INT_L_X0Y95/LV_L7",
                "INT_L_X0Y96/LV_L8",
                "INT_L_X0Y97/LV_L9",
                "INT_L_X0Y98/LV_L10",
                "INT_L_X0Y99/LV_L11",
                "INT_R_X1Y110/NE6END3",
                "INT_R_X1Y110/NN6BEG3",
                "INT_R_X1Y111/NN6A3",
                "INT_R_X1Y112/NN6B3",
                "INT_R_X1Y113/NN6C3",
                "INT_R_X1Y114/NN6D3",
                "INT_R_X1Y115/NN6E3",
                "INT_R_X1Y116/EE2A2",
                "INT_R_X1Y116/NN6END3",
                "INT_R_X1Y116/WW2BEG2",
                "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_NE4BEG3",
                "IO_INT_INTERFACE_L_X0Y106/INT_INTERFACE_NW4A3",
                "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_EE2A2",
                "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_WW2END2",
                "IO_INT_INTERFACE_L_X0Y51/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y51/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y51/IOB_IBUF1",
                "LIOI3_X0Y51/IOI_ILOGIC1_O",
                "LIOI3_X0Y51/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y51/LIOI_I1",
                "LIOI3_X0Y51/LIOI_IBUF1",
                "LIOI3_X0Y51/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y111/L_TERM_INT_NW4BEG3",
                "L_TERM_INT_X2Y121/L_TERM_INT_WW2A2",
                "L_TERM_INT_X2Y54/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y121/VBRK_EE2A2"
            ]
        },
        {
            "name": "dout[0]",
            "node": "INT_L_X2Y133/SW6BEG0",
            "pin": "U12",
            "wire": "VBRK_X9Y139/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_8",
                "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_8",
                "INT_INTERFACE_R_X1Y133/INT_INTERFACE_SW4A0",
                "INT_L_X0Y129/SW6END0",
                "INT_R_X1Y129/SW6E0",
                "INT_R_X1Y130/SW6D0",
                "INT_R_X1Y131/SW6C0",
                "INT_R_X1Y132/SW6B0",
                "INT_R_X1Y133/SW6A0",
                "VBRK_X9Y139/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[1]",
            "node": "INT_L_X2Y135/SW6BEG0",
            "pin": "V12",
            "wire": "VBRK_X9Y141/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_SW4A0_10",
                "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_SW4A0_10",
                "INT_INTERFACE_R_X1Y135/INT_INTERFACE_SW4A0",
                "INT_L_X0Y131/SW6END0",
                "INT_R_X1Y131/SW6E0",
                "INT_R_X1Y132/SW6D0",
                "INT_R_X1Y133/SW6C0",
                "INT_R_X1Y134/SW6B0",
                "INT_R_X1Y135/SW6A0",
                "VBRK_X9Y141/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[2]",
            "node": "INT_L_X2Y137/SW6BEG0",
            "pin": "V10",
            "wire": "VBRK_X9Y143/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_0",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_0",
                "INT_INTERFACE_R_X1Y137/INT_INTERFACE_SW4A0",
                "INT_L_X0Y133/SW6END0",
                "INT_R_X1Y133/SW6E0",
                "INT_R_X1Y134/SW6D0",
                "INT_R_X1Y135/SW6C0",
                "INT_R_X1Y136/SW6B0",
                "INT_R_X1Y137/SW6A0",
                "VBRK_X9Y143/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[3]",
            "node": "INT_L_X2Y139/SW6BEG0",
            "pin": "V11",
            "wire": "VBRK_X9Y145/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_2",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_2",
                "INT_INTERFACE_R_X1Y139/INT_INTERFACE_SW4A0",
                "INT_L_X0Y135/SW6END0",
                "INT_R_X1Y135/SW6E0",
                "INT_R_X1Y136/SW6D0",
                "INT_R_X1Y137/SW6C0",
                "INT_R_X1Y138/SW6B0",
                "INT_R_X1Y139/SW6A0",
                "VBRK_X9Y145/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[4]",
            "node": "INT_L_X2Y141/SW6BEG0",
            "pin": "U14",
            "wire": "VBRK_X9Y147/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_4",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_4",
                "INT_INTERFACE_R_X1Y141/INT_INTERFACE_SW4A0",
                "INT_L_X0Y137/SW6END0",
                "INT_R_X1Y137/SW6E0",
                "INT_R_X1Y138/SW6D0",
                "INT_R_X1Y139/SW6C0",
                "INT_R_X1Y140/SW6B0",
                "INT_R_X1Y141/SW6A0",
                "VBRK_X9Y147/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[5]",
            "node": "INT_L_X2Y143/SW6BEG0",
            "pin": "V14",
            "wire": "VBRK_X9Y149/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_6",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_6",
                "INT_INTERFACE_R_X1Y143/INT_INTERFACE_SW4A0",
                "INT_L_X0Y139/SW6END0",
                "INT_R_X1Y139/SW6E0",
                "INT_R_X1Y140/SW6D0",
                "INT_R_X1Y141/SW6C0",
                "INT_R_X1Y142/SW6B0",
                "INT_R_X1Y143/SW6A0",
                "VBRK_X9Y149/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[6]",
            "node": "INT_L_X2Y145/SW6BEG0",
            "pin": "T13",
            "wire": "VBRK_X9Y151/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_8",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_8",
                "INT_INTERFACE_R_X1Y145/INT_INTERFACE_SW4A0",
                "INT_L_X0Y141/SW6END0",
                "INT_R_X1Y141/SW6E0",
                "INT_R_X1Y142/SW6D0",
                "INT_R_X1Y143/SW6C0",
                "INT_R_X1Y144/SW6B0",
                "INT_R_X1Y145/SW6A0",
                "VBRK_X9Y151/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[7]",
            "node": "INT_L_X2Y147/SW6BEG0",
            "pin": "U13",
            "wire": "VBRK_X9Y153/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_10",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_10",
                "INT_INTERFACE_R_X1Y147/INT_INTERFACE_SW4A0",
                "INT_L_X0Y143/SW6END0",
                "INT_R_X1Y143/SW6E0",
                "INT_R_X1Y144/SW6D0",
                "INT_R_X1Y145/SW6C0",
                "INT_R_X1Y146/SW6B0",
                "INT_R_X1Y147/SW6A0",
                "VBRK_X9Y153/VBRK_SW4A0"
            ]
        }
    ],
    "required_features": [
        "",
        "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
        "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
        "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
        "CLK_BUFG_BOT_R_X60Y48.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_IMUX24_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
        "CLK_BUFG_BOT_R_X60Y48.CLK_BUFG_CK_GCLK0.CLK_BUFG_BUFGCTRL0_O",
        "CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
        "CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y117.GCLK0_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y142.GCLK0_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y38.GCLK0_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
        "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y65.GCLK0_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK0_TOP.CLK_BUFG_REBUF_R_CK_GCLK0_BOT",
        "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y90.GCLK0_ENABLE_BELOW",
        "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
        "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
        "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK0",
        "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK0_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK0_ACTIVE",
        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
        "INT_L_X0Y10.IMUX_L34.SS2END1",
        "INT_L_X0Y10.SL1BEG1.SR1END1",
        "INT_L_X0Y100.LVB_L0.LV_L18",
        "INT_L_X0Y101.SE6BEG0.LV_L0",
        "INT_L_X0Y102.EE2BEG2.NN6END2",
        "INT_L_X0Y103.LV_L18.LV_L0",
        "INT_L_X0Y103.NN6BEG2.LVB_L12",
        "INT_L_X0Y104.EE2BEG2.ER1END2",
        "INT_L_X0Y104.WR1BEG2.NN6END1",
        "INT_L_X0Y105.LV_L18.LV_L0",
        "INT_L_X0Y105.NN2BEG3.NN6END3",
        "INT_L_X0Y106.EE2BEG2.SS6END2",
        "INT_L_X0Y106.NW6BEG3.LV_L18",
        "INT_L_X0Y107.LVB_L12.LV_L0",
        "INT_L_X0Y107.NL1BEG2.NN2END3",
        "INT_L_X0Y107.NN6BEG3.LV_L18",
        "INT_L_X0Y108.EE2BEG2.NL1END2",
        "INT_L_X0Y108.NW6BEG3.LV_L18",
        "INT_L_X0Y109.NR1BEG2.NN6END2",
        "INT_L_X0Y11.SR1BEG1.SS6END0",
        "INT_L_X0Y11.SS6BEG2.SS6END2",
        "INT_L_X0Y110.EE2BEG2.NR1END2",
        "INT_L_X0Y111.LV_L18.LV_L0",
        "INT_L_X0Y112.EE2BEG2.EL1END2",
        "INT_L_X0Y112.SS6BEG2.LVB_L12",
        "INT_L_X0Y112.WL1BEG2.WR1END_S1_0",
        "INT_L_X0Y113.LV_L18.LV_L0",
        "INT_L_X0Y113.NL1BEG2.NN6END3",
        "INT_L_X0Y114.EE2BEG2.NL1END2",
        "INT_L_X0Y115.LV_L18.LV_L0",
        "INT_L_X0Y116.EE2BEG2.EE2END2",
        "INT_L_X0Y117.LV_L18.LV_L0",
        "INT_L_X0Y119.LV_L18.LV_L0",
        "INT_L_X0Y12.SS2BEG1.SR1END1",
        "INT_L_X0Y121.LV_L18.LV_L0",
        "INT_L_X0Y123.LV_L18.LV_L0",
        "INT_L_X0Y125.LV_L18.LV_L0",
        "INT_L_X0Y129.LV_L18.SW6END0",
        "INT_L_X0Y13.SE6BEG0.SS6END0",
        "INT_L_X0Y13.SR1BEG1.SS2END0",
        "INT_L_X0Y13.SS6BEG0.LV_L0",
        "INT_L_X0Y131.LV_L18.SW6END0",
        "INT_L_X0Y133.LV_L18.SW6END0",
        "INT_L_X0Y135.LV_L18.SW6END0",
        "INT_L_X0Y137.LV_L18.SW6END0",
        "INT_L_X0Y139.LV_L18.SW6END0",
        "INT_L_X0Y141.LV_L18.SW6END0",
        "INT_L_X0Y143.LV_L18.SW6END0",
        "INT_L_X0Y15.SS2BEG0.SS6END0",
        "INT_L_X0Y15.SS6BEG0.LV_L0",
        "INT_L_X0Y15.SS6BEG2.SS6END2",
        "INT_L_X0Y17.SS6BEG0.SS6END0",
        "INT_L_X0Y17.SS6BEG2.SS6END2",
        "INT_L_X0Y19.SS6BEG0.SS6END0",
        "INT_L_X0Y21.SS6BEG0.LV_L0",
        "INT_L_X0Y21.SS6BEG2.SS6END2",
        "INT_L_X0Y23.SS6BEG0.LV_L0",
        "INT_L_X0Y23.SS6BEG2.SS6END2",
        "INT_L_X0Y25.SS6BEG0.LV_L0",
        "INT_L_X0Y27.SS6BEG2.SS6END2",
        "INT_L_X0Y29.SS6BEG2.SS6END2",
        "INT_L_X0Y3.FAN_ALT1.SS2END2",
        "INT_L_X0Y3.IMUX_L34.FAN_BOUNCE1",
        "INT_L_X0Y31.LV_L18.LV_L0",
        "INT_L_X0Y33.LV_L18.LV_L0",
        "INT_L_X0Y33.SS6BEG2.SS6END2",
        "INT_L_X0Y35.SS6BEG2.SS6END2",
        "INT_L_X0Y39.LV_L18.LV_L0",
        "INT_L_X0Y39.SS6BEG2.SS6END2",
        "INT_L_X0Y4.IMUX_L34.SS2END1",
        "INT_L_X0Y41.LV_L18.LV_L0",
        "INT_L_X0Y41.SS6BEG2.SS6END2",
        "INT_L_X0Y43.LV_L18.LV_L0",
        "INT_L_X0Y45.SS6BEG2.SS6END2",
        "INT_L_X0Y47.SS6BEG2.SS6END2",
        "INT_L_X0Y49.LV_L18.LV_L0",
        "INT_L_X0Y5.BYP_ALT0.SS2END0",
        "INT_L_X0Y5.IMUX_L34.BYP_BOUNCE0",
        "INT_L_X0Y5.SS2BEG2.SS6END2",
        "INT_L_X0Y51.LV_L18.LV_L0",
        "INT_L_X0Y51.NR1BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y51.SS6BEG2.SS6END2",
        "INT_L_X0Y52.LV_L0.NR1END0",
        "INT_L_X0Y52.NR1BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y53.LV_L0.NR1END0",
        "INT_L_X0Y53.NR1BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y53.SS6BEG2.SS6END2",
        "INT_L_X0Y54.LV_L0.NR1END0",
        "INT_L_X0Y54.NR1BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y55.LV_L0.NR1END0",
        "INT_L_X0Y57.LV_L18.LV_L0",
        "INT_L_X0Y57.SS6BEG2.SS6END2",
        "INT_L_X0Y59.LV_L18.LV_L0",
        "INT_L_X0Y59.SS6BEG2.LVB_L0",
        "INT_L_X0Y6.FAN_ALT1.EL1END3",
        "INT_L_X0Y6.IMUX_L34.FAN_BOUNCE1",
        "INT_L_X0Y6.SS2BEG1.SR1END1",
        "INT_L_X0Y61.LV_L18.LV_L0",
        "INT_L_X0Y63.SS6BEG2.LVB_L0",
        "INT_L_X0Y67.LV_L18.LV_L0",
        "INT_L_X0Y69.LV_L18.LV_L0",
        "INT_L_X0Y7.FAN_ALT1.SS2END2",
        "INT_L_X0Y7.IMUX_L34.FAN_BOUNCE1",
        "INT_L_X0Y7.SR1BEG1.SS2END0",
        "INT_L_X0Y7.SS2BEG0.SS6END0",
        "INT_L_X0Y7.WL1BEG_N3.SW6END0",
        "INT_L_X0Y70.LV_L0.LV_L18",
        "INT_L_X0Y71.LVB_L12.LVB_L0",
        "INT_L_X0Y71.LV_L0.LV_L18",
        "INT_L_X0Y72.LV_L0.LV_L18",
        "INT_L_X0Y73.LV_L0.LV_L18",
        "INT_L_X0Y75.LVB_L12.LVB_L0",
        "INT_L_X0Y75.LV_L18.LV_L0",
        "INT_L_X0Y75.NN6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y76.NN6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y77.LV_L18.LV_L0",
        "INT_L_X0Y77.NN6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y78.NN6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y79.LV_L18.LV_L0",
        "INT_L_X0Y8.IMUX_L34.WW2END0",
        "INT_L_X0Y81.LV_L0.NN6END0",
        "INT_L_X0Y82.LV_L0.NN6END0",
        "INT_L_X0Y83.LVB_L12.LVB_L0",
        "INT_L_X0Y83.LV_L0.NN6END0",
        "INT_L_X0Y84.LVB_L0.LV_L0",
        "INT_L_X0Y84.LV_L0.NN6END0",
        "INT_L_X0Y85.LV_L18.LV_L0",
        "INT_L_X0Y87.LVB_L12.LVB_L0",
        "INT_L_X0Y87.LV_L18.LV_L0",
        "INT_L_X0Y88.LV_L0.LV_L18",
        "INT_L_X0Y89.LV_L0.LV_L18",
        "INT_L_X0Y9.IMUX_L34.SL1END1",
        "INT_L_X0Y9.SS2BEG0.SS6END0",
        "INT_L_X0Y9.SS2BEG2.SS6END2",
        "INT_L_X0Y90.LV_L0.LV_L18",
        "INT_L_X0Y91.LVB_L0.LV_L18",
        "INT_L_X0Y92.NN6BEG1.LV_L9",
        "INT_L_X0Y93.LV_L18.LV_L0",
        "INT_L_X0Y95.LVB_L12.LVB_L0",
        "INT_L_X0Y95.LV_L18.LV_L0",
        "INT_L_X0Y96.NN6BEG2.LVB_L12",
        "INT_L_X0Y97.LV_L18.LV_L0",
        "INT_L_X0Y98.NN6BEG1.NN6END1",
        "INT_L_X0Y99.LVB_L12.LV_L0",
        "INT_L_X0Y99.NN6BEG3.LV_L18",
        "INT_L_X0Y99.SE6BEG0.LOGIC_OUTS_L18",
        "INT_L_X10Y79.EE2BEG0.SE6END0",
        "INT_L_X18Y79.SE6BEG0.EE2END0",
        "INT_L_X20Y75.SE6BEG0.SE6END0",
        "INT_L_X22Y47.SE2BEG0.SS6END0",
        "INT_L_X22Y53.SS6BEG0.SS6END0",
        "INT_L_X22Y59.SS6BEG0.SS6END0",
        "INT_L_X22Y65.SS6BEG0.SS6END0",
        "INT_L_X22Y71.SS6BEG0.SE6END0",
        "INT_L_X2Y11.SW6BEG0.SS6END0",
        "INT_L_X2Y17.SS6BEG0.LV_L0",
        "INT_L_X2Y35.LV_L18.LV_L0",
        "INT_L_X2Y53.LV_L18.LV_L0",
        "INT_L_X2Y71.LV_L18.LV_L0",
        "INT_L_X2Y8.WW2BEG0.SL1END0",
        "INT_L_X2Y89.LV_L18.SW6END0",
        "INT_L_X2Y9.SL1BEG0.SE6END0",
        "INT_L_X2Y95.SE6BEG0.SE6END0",
        "INT_L_X2Y97.SE6BEG0.SE6END0",
        "INT_L_X4Y91.SE6BEG0.SE6END0",
        "INT_L_X4Y93.SW6BEG0.SE6END0",
        "INT_L_X6Y87.SE6BEG0.SE6END0",
        "INT_L_X8Y83.SE6BEG0.SE6END0",
        "INT_R_X1Y110.NN6BEG3.NE6END3",
        "INT_R_X1Y112.WR1BEG_S0.NE6END3",
        "INT_R_X1Y116.WW2BEG2.NN6END3",
        "INT_R_X23Y46.IMUX24.SE2END0",
        "LIOB33_SING_X0Y99.IOB_Y1.IN_ONLY",
        "LIOB33_SING_X0Y99.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_SING_X0Y99.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_SING_X0Y99.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_SING_X0Y99.IOB_Y1.SLEW.FAST",
        "LIOB33_SING_X0Y99.IOB_Y1.ZINV_D",
        "LIOB33_X0Y3.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y3.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y3.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y3.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y3.IOB_Y0.SLEW.SLOW",
        "LIOB33_X0Y3.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y3.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y3.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y3.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y3.IOB_Y1.SLEW.SLOW",
        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y5.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y5.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y5.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y5.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y5.IOB_Y0.SLEW.SLOW",
        "LIOB33_X0Y5.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y5.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y5.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y5.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y5.IOB_Y1.SLEW.SLOW",
        "LIOB33_X0Y51.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y51.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y51.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y51.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y51.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y51.IOB_Y0.ZINV_D",
        "LIOB33_X0Y51.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y51.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y51.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y51.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y51.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y51.IOB_Y1.ZINV_D",
        "LIOB33_X0Y53.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y53.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y53.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y53.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y53.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y53.IOB_Y0.ZINV_D",
        "LIOB33_X0Y53.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y53.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y53.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y53.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y53.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y53.IOB_Y1.ZINV_D",
        "LIOB33_X0Y7.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y7.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y7.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y7.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y7.IOB_Y0.SLEW.SLOW",
        "LIOB33_X0Y7.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y7.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y7.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y7.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y7.IOB_Y1.SLEW.SLOW",
        "LIOB33_X0Y75.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y75.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y75.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y75.IOB_Y0.ZINV_D",
        "LIOB33_X0Y75.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y75.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y75.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y75.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y75.IOB_Y1.ZINV_D",
        "LIOB33_X0Y77.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y77.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y77.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y77.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y77.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y77.IOB_Y0.ZINV_D",
        "LIOB33_X0Y77.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y77.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y77.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y77.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y77.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y77.IOB_Y1.ZINV_D",
        "LIOB33_X0Y9.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y9.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y9.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y9.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y9.IOB_Y0.SLEW.SLOW",
        "LIOB33_X0Y9.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y9.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y9.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y9.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y9.IOB_Y1.SLEW.SLOW"
    ]
}