{
    "info": {
        "GRID_X_MAX": 58,
        "GRID_X_MIN": 10,
        "GRID_Y_MAX": 51,
        "GRID_Y_MIN": 0
    },
    "ports": [
        {
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "E3",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_L_X0Y104/EE2BEG2",
            "pin": "A8",
            "wire": "VBRK_X9Y109/VBRK_EE2A2",
            "wires_outside_roi": [
                "BRKH_INT_X0Y99/BRKH_INT_LVB_L4",
                "BRKH_INT_X0Y99/BRKH_INT_NN6C2",
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_3",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_4",
                "HCLK_L_X4Y130/HCLK_LV16",
                "INT_INTERFACE_R_X1Y104/INT_INTERFACE_EE2A2",
                "INT_L_X0Y100/LVB_L4",
                "INT_L_X0Y100/NN6D2",
                "INT_L_X0Y101/LVB_L5",
                "INT_L_X0Y101/NN6E2",
                "INT_L_X0Y102/LVB_L6",
                "INT_L_X0Y102/NN2BEG2",
                "INT_L_X0Y102/NN6END2",
                "INT_L_X0Y103/LVB_L7",
                "INT_L_X0Y103/NN2A2",
                "INT_L_X0Y104/EE2BEG2",
                "INT_L_X0Y104/LVB_L8",
                "INT_L_X0Y104/NN2END2",
                "INT_L_X0Y105/LVB_L9",
                "INT_L_X0Y106/LVB_L10",
                "INT_L_X0Y107/LVB_L11",
                "INT_L_X0Y108/LVB_L12",
                "INT_L_X0Y108/LV_L0",
                "INT_L_X0Y109/LV_L1",
                "INT_L_X0Y110/LV_L2",
                "INT_L_X0Y111/LV_L3",
                "INT_L_X0Y112/LV_L4",
                "INT_L_X0Y113/LV_L5",
                "INT_L_X0Y114/LV_L6",
                "INT_L_X0Y115/LV_L7",
                "INT_L_X0Y116/LV_L8",
                "INT_L_X0Y117/LV_L9",
                "INT_L_X0Y118/LV_L10",
                "INT_L_X0Y119/LV_L11",
                "INT_L_X0Y120/LV_L12",
                "INT_L_X0Y121/LV_L13",
                "INT_L_X0Y122/LV_L14",
                "INT_L_X0Y123/LV_L15",
                "INT_L_X0Y124/LV_L16",
                "INT_L_X0Y125/LOGIC_OUTS_L18",
                "INT_L_X0Y125/LV_L17",
                "INT_L_X0Y125/NR1BEG0",
                "INT_L_X0Y126/LV_L18",
                "INT_L_X0Y126/NR1END0",
                "INT_L_X0Y96/LVB_L0",
                "INT_L_X0Y96/NN6BEG2",
                "INT_L_X0Y97/LVB_L1",
                "INT_L_X0Y97/NN6A2",
                "INT_L_X0Y98/LVB_L2",
                "INT_L_X0Y98/NN6B2",
                "INT_L_X0Y99/LVB_L3",
                "INT_L_X0Y99/NN6C2",
                "INT_R_X1Y104/EE2A2",
                "IO_INT_INTERFACE_L_X0Y125/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y125/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y125/IOB_IBUF1",
                "LIOI3_X0Y125/IOI_ILOGIC1_O",
                "LIOI3_X0Y125/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y125/LIOI_I1",
                "LIOI3_X0Y125/LIOI_IBUF1",
                "LIOI3_X0Y125/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y131/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y109/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[1]",
            "node": "INT_L_X0Y108/EE2BEG2",
            "pin": "C11",
            "wire": "VBRK_X9Y113/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_7",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_8",
                "INT_INTERFACE_R_X1Y108/INT_INTERFACE_EE2A2",
                "INT_L_X0Y108/EE2BEG2",
                "INT_L_X0Y108/SE6END2",
                "INT_L_X0Y108/SW6E2",
                "INT_L_X0Y109/SW6D2",
                "INT_L_X0Y110/SW6C2",
                "INT_L_X0Y111/SW6B2",
                "INT_L_X0Y112/SW6A2",
                "INT_L_X0Y123/EL1BEG3",
                "INT_L_X0Y124/EL1BEG_N3",
                "INT_L_X0Y124/LOGIC_OUTS_L18",
                "INT_R_X1Y108/EE2A2",
                "INT_R_X1Y112/LVB0",
                "INT_R_X1Y112/SW6BEG2",
                "INT_R_X1Y113/LVB1",
                "INT_R_X1Y114/LVB2",
                "INT_R_X1Y115/LVB3",
                "INT_R_X1Y116/LVB4",
                "INT_R_X1Y117/LVB5",
                "INT_R_X1Y118/LVB6",
                "INT_R_X1Y119/LVB7",
                "INT_R_X1Y120/LVB8",
                "INT_R_X1Y121/LVB9",
                "INT_R_X1Y122/LVB10",
                "INT_R_X1Y123/EL1END3",
                "INT_R_X1Y123/LVB11",
                "INT_R_X1Y123/NR1BEG3",
                "INT_R_X1Y124/LVB12",
                "INT_R_X1Y124/NR1END3",
                "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_SE4C2",
                "IO_INT_INTERFACE_L_X0Y108/INT_INTERFACE_SW4END2",
                "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y123/IOB_IBUF0",
                "LIOI3_X0Y123/IOI_ILOGIC0_O",
                "LIOI3_X0Y123/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y123/LIOI_I0",
                "LIOI3_X0Y123/LIOI_IBUF0",
                "LIOI3_X0Y123/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y113/L_TERM_INT_SW4C2",
                "L_TERM_INT_X2Y129/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y113/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[2]",
            "node": "INT_L_X0Y112/EE2BEG2",
            "pin": "C10",
            "wire": "VBRK_X9Y117/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_11",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_12",
                "INT_INTERFACE_R_X1Y112/INT_INTERFACE_EE2A2",
                "INT_L_X0Y112/EE2BEG2",
                "INT_L_X0Y112/EL1END2",
                "INT_L_X0Y112/WL1BEG2",
                "INT_L_X0Y112/WL1END3",
                "INT_L_X0Y113/SE6E0",
                "INT_L_X0Y113/WL1END_N1_3",
                "INT_L_X0Y114/SE6D0",
                "INT_L_X0Y115/SE6C0",
                "INT_L_X0Y116/SE6B0",
                "INT_L_X0Y117/SE6A0",
                "INT_L_X0Y117/SS6END0",
                "INT_L_X0Y117/SW6BEG0",
                "INT_L_X0Y118/SS6E0",
                "INT_L_X0Y119/SS6D0",
                "INT_L_X0Y120/SS6C0",
                "INT_L_X0Y121/SS6B0",
                "INT_L_X0Y122/SS6A0",
                "INT_L_X0Y123/LOGIC_OUTS_L18",
                "INT_L_X0Y123/SS6BEG0",
                "INT_R_X1Y112/EE2A2",
                "INT_R_X1Y112/WL1BEG3",
                "INT_R_X1Y113/SE6END0",
                "INT_R_X1Y113/WL1BEG_N3",
                "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_EL1BEG2",
                "IO_INT_INTERFACE_L_X0Y112/INT_INTERFACE_WL1END2",
                "IO_INT_INTERFACE_L_X0Y117/INT_INTERFACE_SE4BEG0",
                "IO_INT_INTERFACE_L_X0Y117/INT_INTERFACE_SW4A0",
                "IO_INT_INTERFACE_L_X0Y123/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y123/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y123/IOB_IBUF1",
                "LIOI3_X0Y123/IOI_ILOGIC1_O",
                "LIOI3_X0Y123/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y123/LIOI_I1",
                "LIOI3_X0Y123/LIOI_IBUF1",
                "LIOI3_X0Y123/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y117/L_TERM_INT_WL1BEG2",
                "L_TERM_INT_X2Y122/L_TERM_INT_SW4BEG0",
                "L_TERM_INT_X2Y128/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y117/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[3]",
            "node": "INT_L_X0Y116/EE2BEG2",
            "pin": "A10",
            "wire": "VBRK_X9Y121/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_3",
                "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_0",
                "INT_INTERFACE_R_X1Y116/INT_INTERFACE_EE2A2",
                "INT_L_X0Y116/EE2BEG2",
                "INT_L_X0Y116/EL1END2",
                "INT_L_X0Y116/SE2END3",
                "INT_L_X0Y116/SW2A3",
                "INT_L_X0Y116/WL1BEG2",
                "INT_L_X0Y117/SW2BEG3",
                "INT_L_X0Y117/WL1END3",
                "INT_L_X0Y118/SE6E0",
                "INT_L_X0Y118/WL1END_N1_3",
                "INT_L_X0Y119/SE6D0",
                "INT_L_X0Y120/SE6C0",
                "INT_L_X0Y121/SE6B0",
                "INT_L_X0Y122/LOGIC_OUTS_L18",
                "INT_L_X0Y122/SE6A0",
                "INT_L_X0Y122/SW6BEG0",
                "INT_R_X1Y116/EE2A2",
                "INT_R_X1Y117/WL1BEG3",
                "INT_R_X1Y118/SE6END0",
                "INT_R_X1Y118/WL1BEG_N3",
                "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_EL1BEG2",
                "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_SE2A3",
                "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_SW2A3",
                "IO_INT_INTERFACE_L_X0Y116/INT_INTERFACE_WL1END2",
                "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_SE4BEG0",
                "IO_INT_INTERFACE_L_X0Y122/INT_INTERFACE_SW4A0",
                "LIOB33_X0Y121/IOB_IBUF0",
                "LIOI3_X0Y121/IOI_ILOGIC0_O",
                "LIOI3_X0Y121/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y121/LIOI_I0",
                "LIOI3_X0Y121/LIOI_IBUF0",
                "LIOI3_X0Y121/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y121/L_TERM_INT_SW2BEG3",
                "L_TERM_INT_X2Y121/L_TERM_INT_WL1BEG2",
                "L_TERM_INT_X2Y127/L_TERM_INT_SW4BEG0",
                "L_TERM_INT_X2Y127/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y121/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[4]",
            "node": "INT_L_X0Y120/EE2BEG2",
            "pin": "C9",
            "wire": "VBRK_X9Y125/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_7",
                "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_4",
                "HCLK_L_X4Y130/HCLK_SS6D0",
                "INT_INTERFACE_R_X1Y120/INT_INTERFACE_EE2A2",
                "INT_L_X0Y120/EE2BEG2",
                "INT_L_X0Y120/EL1END2",
                "INT_L_X0Y120/SL1END3",
                "INT_L_X0Y120/WL1BEG2",
                "INT_L_X0Y121/EL1END3",
                "INT_L_X0Y121/SL1BEG3",
                "INT_L_X0Y121/WL1BEG3",
                "INT_L_X0Y122/SS6END0",
                "INT_L_X0Y122/WL1BEG_N3",
                "INT_L_X0Y123/SS6E0",
                "INT_L_X0Y124/SS6D0",
                "INT_L_X0Y125/SS6C0",
                "INT_L_X0Y126/SS6B0",
                "INT_L_X0Y127/SS6A0",
                "INT_L_X0Y128/LOGIC_OUTS_L18",
                "INT_L_X0Y128/SS6BEG0",
                "INT_R_X1Y120/EE2A2",
                "IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_EL1BEG2",
                "IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_WL1END2",
                "IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_EL1BEG3",
                "IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_WL1END3",
                "IO_INT_INTERFACE_L_X0Y128/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y128/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y127/IOB_IBUF0",
                "LIOI3_X0Y127/IOI_ILOGIC0_O",
                "LIOI3_X0Y127/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y127/LIOI_I0",
                "LIOI3_X0Y127/LIOI_IBUF0",
                "LIOI3_X0Y127/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y125/L_TERM_INT_WL1BEG2",
                "L_TERM_INT_X2Y126/L_TERM_INT_WR1BEG2",
                "L_TERM_INT_X2Y134/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y125/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[5]",
            "node": "INT_L_X0Y124/EE2BEG2",
            "pin": "B9",
            "wire": "VBRK_X9Y129/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_EE2A2_11",
                "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_EE2A2_8",
                "HCLK_L_X4Y130/HCLK_SS2A3",
                "HCLK_L_X4Y130/HCLK_SS2END_N0_3",
                "INT_INTERFACE_R_X1Y124/INT_INTERFACE_EE2A2",
                "INT_L_X0Y124/EE2BEG2",
                "INT_L_X0Y124/EL1END2",
                "INT_L_X0Y124/SS2END3",
                "INT_L_X0Y124/WL1BEG2",
                "INT_L_X0Y125/SS2A3",
                "INT_L_X0Y125/SS2END_N0_3",
                "INT_L_X0Y126/EL1END3",
                "INT_L_X0Y126/SS2BEG3",
                "INT_L_X0Y126/WL1BEG3",
                "INT_L_X0Y127/LOGIC_OUTS_L18",
                "INT_L_X0Y127/WL1BEG_N3",
                "INT_R_X1Y124/EE2A2",
                "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_EL1BEG2",
                "IO_INT_INTERFACE_L_X0Y124/INT_INTERFACE_WL1END2",
                "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_EL1BEG3",
                "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_WL1END3",
                "IO_INT_INTERFACE_L_X0Y127/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y127/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y127/IOB_IBUF1",
                "LIOI3_X0Y127/IOI_ILOGIC1_O",
                "LIOI3_X0Y127/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y127/LIOI_I1",
                "LIOI3_X0Y127/LIOI_IBUF1",
                "LIOI3_X0Y127/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y129/L_TERM_INT_WL1BEG2",
                "L_TERM_INT_X2Y132/L_TERM_INT_WR1BEG2",
                "L_TERM_INT_X2Y133/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y129/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[6]",
            "node": "INT_L_X0Y128/EE2BEG2",
            "pin": "B8",
            "wire": "VBRK_X9Y134/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_EE2A2_3",
                "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_EE2A2_3",
                "INT_INTERFACE_R_X1Y128/INT_INTERFACE_EE2A2",
                "INT_L_X0Y126/LOGIC_OUTS_L18",
                "INT_L_X0Y126/NR1BEG0",
                "INT_L_X0Y127/NL1BEG2",
                "INT_L_X0Y127/NL1BEG_N3",
                "INT_L_X0Y127/NR1END0",
                "INT_L_X0Y128/EE2BEG2",
                "INT_L_X0Y128/NL1END2",
                "INT_R_X1Y128/EE2A2",
                "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y126/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y125/IOB_IBUF0",
                "LIOI3_X0Y125/IOI_ILOGIC0_O",
                "LIOI3_X0Y125/IOI_LOGIC_OUTS18_1",
                "LIOI3_X0Y125/LIOI_I0",
                "LIOI3_X0Y125/LIOI_IBUF0",
                "LIOI3_X0Y125/LIOI_ILOGIC0_D",
                "L_TERM_INT_X2Y132/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y134/VBRK_EE2A2"
            ]
        },
        {
            "name": "din[7]",
            "node": "INT_L_X0Y132/EE2BEG2",
            "pin": "D9",
            "wire": "VBRK_X9Y138/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y137/CMT_FIFO_EE2A2_7",
                "CMT_TOP_R_UPPER_B_X8Y135/CMT_TOP_EE2A2_7",
                "INT_INTERFACE_R_X1Y132/INT_INTERFACE_EE2A2",
                "INT_L_X0Y132/EE2BEG2",
                "INT_L_X0Y132/EL1END2",
                "INT_L_X0Y132/WL1BEG2",
                "INT_L_X0Y132/WL1END3",
                "INT_L_X0Y133/SE6E0",
                "INT_L_X0Y133/WL1END_N1_3",
                "INT_L_X0Y134/SE6D0",
                "INT_L_X0Y135/SE6C0",
                "INT_L_X0Y136/SE6B0",
                "INT_L_X0Y137/LOGIC_OUTS_L18",
                "INT_L_X0Y137/SE6A0",
                "INT_L_X0Y137/SW6BEG0",
                "INT_R_X1Y132/EE2A2",
                "INT_R_X1Y132/WL1BEG3",
                "INT_R_X1Y133/SE6END0",
                "INT_R_X1Y133/WL1BEG_N3",
                "IO_INT_INTERFACE_L_X0Y132/INT_INTERFACE_EL1BEG2",
                "IO_INT_INTERFACE_L_X0Y132/INT_INTERFACE_WL1END2",
                "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_SE4BEG0",
                "IO_INT_INTERFACE_L_X0Y137/INT_INTERFACE_SW4A0",
                "LIOB33_X0Y137/IOB_IBUF1",
                "LIOI3_TBYTETERM_X0Y137/IOI_ILOGIC1_O",
                "LIOI3_TBYTETERM_X0Y137/IOI_LOGIC_OUTS18_0",
                "LIOI3_TBYTETERM_X0Y137/LIOI_I1",
                "LIOI3_TBYTETERM_X0Y137/LIOI_IBUF1",
                "LIOI3_TBYTETERM_X0Y137/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y138/L_TERM_INT_WL1BEG2",
                "L_TERM_INT_X2Y143/L_TERM_INT_SW4BEG0",
                "L_TERM_INT_X2Y143/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y138/VBRK_EE2A2"
            ]
        },
        {
            "name": "dout[0]",
            "node": "INT_R_X23Y117/LH12",
            "pin": "H5",
            "wire": "VBRK_X61Y122/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y117/CLBLL_LH12",
                "CLBLL_L_X26Y117/CLBLL_LH10",
                "CLBLL_R_X31Y117/CLBLL_LH6",
                "CLBLM_L_X32Y117/CLBLM_LH6",
                "CLBLM_L_X36Y117/CLBLM_LH2",
                "CLBLM_R_X25Y117/CLBLM_LH10",
                "CLBLM_R_X33Y117/CLBLM_LH4",
                "CLBLM_R_X35Y117/CLBLM_LH2",
                "CLK_FEED_X60Y122/CLK_FEED_LH12",
                "DSP_L_X34Y115/DSP_LH4_2",
                "INT_INTERFACE_L_X34Y117/INT_INTERFACE_LH4",
                "INT_INTERFACE_R_X23Y117/INT_INTERFACE_LH12",
                "INT_L_X24Y117/LH11",
                "INT_L_X26Y117/LH9",
                "INT_L_X30Y117/LH7",
                "INT_L_X32Y117/LH5",
                "INT_L_X34Y117/LH3",
                "INT_L_X36Y117/LH1",
                "INT_R_X25Y117/LH10",
                "INT_R_X27Y117/LH8",
                "INT_R_X31Y117/LH6",
                "INT_R_X33Y117/LH4",
                "INT_R_X35Y117/LH2",
                "INT_R_X37Y117/LH0",
                "PCIE_BOT_X71Y115/PCIE_LH8_17",
                "PCIE_INT_INTERFACE_L_X30Y117/INT_INTERFACE_LH8",
                "PCIE_INT_INTERFACE_R_X27Y117/INT_INTERFACE_LH8",
                "VBRK_X61Y122/VBRK_LH12",
                "VBRK_X66Y122/VBRK_LH10",
                "VBRK_X80Y122/VBRK_LH6",
                "VBRK_X85Y122/VBRK_LH4"
            ]
        },
        {
            "name": "dout[1]",
            "node": "INT_R_X23Y121/LH12",
            "pin": "J5",
            "wire": "VBRK_X61Y126/VBRK_LH12",
            "wires_outside_roi": [
                "CLBLL_L_X24Y121/CLBLL_LH12",
                "CLBLL_L_X26Y121/CLBLL_LH10",
                "CLBLL_R_X31Y121/CLBLL_LH6",
                "CLBLM_L_X32Y121/CLBLM_LH6",
                "CLBLM_L_X36Y121/CLBLM_LH2",
                "CLBLM_R_X25Y121/CLBLM_LH10",
                "CLBLM_R_X33Y121/CLBLM_LH4",
                "CLBLM_R_X35Y121/CLBLM_LH2",
                "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_0",
                "DSP_L_X34Y120/DSP_LH4_1",
                "INT_INTERFACE_L_X34Y121/INT_INTERFACE_LH4",
                "INT_INTERFACE_R_X23Y121/INT_INTERFACE_LH12",
                "INT_L_X24Y121/LH11",
                "INT_L_X26Y121/LH9",
                "INT_L_X30Y121/LH7",
                "INT_L_X32Y121/LH5",
                "INT_L_X34Y121/LH3",
                "INT_L_X36Y121/LH1",
                "INT_R_X25Y121/LH10",
                "INT_R_X27Y121/LH8",
                "INT_R_X31Y121/LH6",
                "INT_R_X33Y121/LH4",
                "INT_R_X35Y121/LH2",
                "INT_R_X37Y121/LH0",
                "PCIE_INT_INTERFACE_L_X30Y121/INT_INTERFACE_LH8",
                "PCIE_INT_INTERFACE_R_X27Y121/INT_INTERFACE_LH8",
                "PCIE_TOP_X71Y125/PCIE_LH8_1",
                "VBRK_X61Y126/VBRK_LH12",
                "VBRK_X66Y126/VBRK_LH10",
                "VBRK_X80Y126/VBRK_LH6",
                "VBRK_X85Y126/VBRK_LH4"
            ]
        },
        {
            "name": "dout[2]",
            "node": "INT_L_X2Y117/SW6BEG0",
            "pin": "T9",
            "wire": "VBRK_X9Y122/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_4",
                "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_1",
                "INT_INTERFACE_R_X1Y117/INT_INTERFACE_SW4A0",
                "INT_L_X0Y113/SW6END0",
                "INT_R_X1Y113/SW6E0",
                "INT_R_X1Y114/SW6D0",
                "INT_R_X1Y115/SW6C0",
                "INT_R_X1Y116/SW6B0",
                "INT_R_X1Y117/SW6A0",
                "VBRK_X9Y122/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[3]",
            "node": "INT_L_X2Y121/SW6BEG0",
            "pin": "T10",
            "wire": "VBRK_X9Y126/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y124/CMT_FIFO_SW4A0_8",
                "CMT_TOP_R_LOWER_T_X8Y122/CMT_TOP_SW4A0_5",
                "INT_INTERFACE_R_X1Y121/INT_INTERFACE_SW4A0",
                "INT_L_X0Y117/SW6END0",
                "INT_R_X1Y117/SW6E0",
                "INT_R_X1Y118/SW6D0",
                "INT_R_X1Y119/SW6C0",
                "INT_R_X1Y120/SW6B0",
                "INT_R_X1Y121/SW6A0",
                "VBRK_X9Y126/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[4]",
            "node": "INT_R_X23Y125/LH12",
            "pin": "F6",
            "wire": "VBRK_X61Y131/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y125/INT_INTERFACE_LH6",
                "BRAM_L_X30Y125/BRAM_LH6_0",
                "CLBLL_L_X24Y125/CLBLL_LH12",
                "CLBLL_L_X26Y125/CLBLL_LH10",
                "CLBLL_L_X28Y125/CLBLL_LH8",
                "CLBLL_R_X31Y125/CLBLL_LH4",
                "CLBLM_L_X32Y125/CLBLM_LH4",
                "CLBLM_R_X25Y125/CLBLM_LH10",
                "CLBLM_R_X27Y125/CLBLM_LH8",
                "CLBLM_R_X29Y125/CLBLM_LH6",
                "CLBLM_R_X33Y125/CLBLM_LH2",
                "CLK_HROW_TOP_R_X60Y130/CLK_HROW_LH12_4",
                "DSP_L_X34Y125/DSP_LH2_0",
                "INT_INTERFACE_L_X34Y125/INT_INTERFACE_LH2",
                "INT_INTERFACE_R_X23Y125/INT_INTERFACE_LH12",
                "INT_L_X24Y125/LH11",
                "INT_L_X26Y125/LH9",
                "INT_L_X28Y125/LH7",
                "INT_L_X30Y125/LH5",
                "INT_L_X32Y125/LH3",
                "INT_L_X34Y125/LH1",
                "INT_R_X25Y125/LH10",
                "INT_R_X27Y125/LH8",
                "INT_R_X29Y125/LH6",
                "INT_R_X31Y125/LH4",
                "INT_R_X33Y125/LH2",
                "INT_R_X35Y125/LH0",
                "VBRK_X61Y131/VBRK_LH12",
                "VBRK_X66Y131/VBRK_LH10",
                "VBRK_X80Y131/VBRK_LH4",
                "VBRK_X85Y131/VBRK_LH2"
            ]
        },
        {
            "name": "dout[5]",
            "node": "INT_R_X23Y129/LH12",
            "pin": "J4",
            "wire": "VBRK_X61Y135/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y129/INT_INTERFACE_LH6",
                "BRAM_L_X30Y125/BRAM_LH6_4",
                "CLBLL_L_X24Y129/CLBLL_LH12",
                "CLBLL_L_X26Y129/CLBLL_LH10",
                "CLBLL_L_X28Y129/CLBLL_LH8",
                "CLBLL_R_X31Y129/CLBLL_LH4",
                "CLBLM_L_X32Y129/CLBLM_LH4",
                "CLBLM_R_X25Y129/CLBLM_LH10",
                "CLBLM_R_X27Y129/CLBLM_LH8",
                "CLBLM_R_X29Y129/CLBLM_LH6",
                "CLBLM_R_X33Y129/CLBLM_LH2",
                "CLK_FEED_X60Y135/CLK_FEED_LH12",
                "DSP_L_X34Y125/DSP_LH2_4",
                "INT_INTERFACE_L_X34Y129/INT_INTERFACE_LH2",
                "INT_INTERFACE_R_X23Y129/INT_INTERFACE_LH12",
                "INT_L_X24Y129/LH11",
                "INT_L_X26Y129/LH9",
                "INT_L_X28Y129/LH7",
                "INT_L_X30Y129/LH5",
                "INT_L_X32Y129/LH3",
                "INT_L_X34Y129/LH1",
                "INT_R_X25Y129/LH10",
                "INT_R_X27Y129/LH8",
                "INT_R_X29Y129/LH6",
                "INT_R_X31Y129/LH4",
                "INT_R_X33Y129/LH2",
                "INT_R_X35Y129/LH0",
                "VBRK_X61Y135/VBRK_LH12",
                "VBRK_X66Y135/VBRK_LH10",
                "VBRK_X80Y135/VBRK_LH4",
                "VBRK_X85Y135/VBRK_LH2"
            ]
        },
        {
            "name": "dout[6]",
            "node": "INT_R_X23Y133/LH12",
            "pin": "J2",
            "wire": "VBRK_X61Y139/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y133/INT_INTERFACE_LH6",
                "BRAM_L_X30Y130/BRAM_LH6_3",
                "CLBLL_L_X24Y133/CLBLL_LH12",
                "CLBLL_L_X26Y133/CLBLL_LH10",
                "CLBLL_L_X28Y133/CLBLL_LH8",
                "CLBLL_R_X31Y133/CLBLL_LH4",
                "CLBLM_L_X32Y133/CLBLM_LH4",
                "CLBLM_R_X25Y133/CLBLM_LH10",
                "CLBLM_R_X27Y133/CLBLM_LH8",
                "CLBLM_R_X29Y133/CLBLM_LH6",
                "CLBLM_R_X33Y133/CLBLM_LH2",
                "CLK_FEED_X60Y139/CLK_FEED_LH12",
                "DSP_L_X34Y130/DSP_LH2_3",
                "INT_INTERFACE_L_X34Y133/INT_INTERFACE_LH2",
                "INT_INTERFACE_R_X23Y133/INT_INTERFACE_LH12",
                "INT_L_X24Y133/LH11",
                "INT_L_X26Y133/LH9",
                "INT_L_X28Y133/LH7",
                "INT_L_X30Y133/LH5",
                "INT_L_X32Y133/LH3",
                "INT_L_X34Y133/LH1",
                "INT_R_X25Y133/LH10",
                "INT_R_X27Y133/LH8",
                "INT_R_X29Y133/LH6",
                "INT_R_X31Y133/LH4",
                "INT_R_X33Y133/LH2",
                "INT_R_X35Y133/LH0",
                "VBRK_X61Y139/VBRK_LH12",
                "VBRK_X66Y139/VBRK_LH10",
                "VBRK_X80Y139/VBRK_LH4",
                "VBRK_X85Y139/VBRK_LH2"
            ]
        },
        {
            "name": "dout[7]",
            "node": "INT_R_X23Y137/LH12",
            "pin": "H6",
            "wire": "VBRK_X61Y143/VBRK_LH12",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_L_X30Y137/INT_INTERFACE_LH6",
                "BRAM_L_X30Y135/BRAM_LH6_2",
                "CLBLL_L_X24Y137/CLBLL_LH12",
                "CLBLL_L_X26Y137/CLBLL_LH10",
                "CLBLL_L_X28Y137/CLBLL_LH8",
                "CLBLL_R_X31Y137/CLBLL_LH4",
                "CLBLM_L_X32Y137/CLBLM_LH4",
                "CLBLM_R_X25Y137/CLBLM_LH10",
                "CLBLM_R_X27Y137/CLBLM_LH8",
                "CLBLM_R_X29Y137/CLBLM_LH6",
                "CLBLM_R_X33Y137/CLBLM_LH2",
                "CLK_BUFG_REBUF_X60Y142/CLK_BUFG_REBUF_LH12_1",
                "DSP_L_X34Y135/DSP_LH2_2",
                "INT_INTERFACE_L_X34Y137/INT_INTERFACE_LH2",
                "INT_INTERFACE_R_X23Y137/INT_INTERFACE_LH12",
                "INT_L_X24Y137/LH11",
                "INT_L_X26Y137/LH9",
                "INT_L_X28Y137/LH7",
                "INT_L_X30Y137/LH5",
                "INT_L_X32Y137/LH3",
                "INT_L_X34Y137/LH1",
                "INT_R_X25Y137/LH10",
                "INT_R_X27Y137/LH8",
                "INT_R_X29Y137/LH6",
                "INT_R_X31Y137/LH4",
                "INT_R_X33Y137/LH2",
                "INT_R_X35Y137/LH0",
                "VBRK_X61Y143/VBRK_LH12",
                "VBRK_X66Y143/VBRK_LH10",
                "VBRK_X80Y143/VBRK_LH4",
                "VBRK_X85Y143/VBRK_LH2"
            ]
        }
    ],
    "required_features": [
        "",
        "CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
        "CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y142.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y38.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
        "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
        "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O",
        "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
        "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
        "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK16",
        "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_CK_IN_R0_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
        "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
        "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
        "INT_L_X0Y1.IMUX_L34.SL1END1",
        "INT_L_X0Y102.NN2BEG2.NN6END2",
        "INT_L_X0Y104.EE2BEG2.NN2END2",
        "INT_L_X0Y108.EE2BEG2.SE6END2",
        "INT_L_X0Y108.LVB_L12.LV_L0",
        "INT_L_X0Y11.SS6BEG0.SS6END0",
        "INT_L_X0Y112.EE2BEG2.EL1END2",
        "INT_L_X0Y112.WL1BEG2.WL1END3",
        "INT_L_X0Y113.LV_L18.SW6END0",
        "INT_L_X0Y116.EE2BEG2.EL1END2",
        "INT_L_X0Y116.EE2BEG3.SE2END3",
        "INT_L_X0Y116.WL1BEG2.SE2END3",
        "INT_L_X0Y117.LV_L18.SW6END0",
        "INT_L_X0Y117.SW2BEG3.WL1END3",
        "INT_L_X0Y117.SW6BEG0.SS6END0",
        "INT_L_X0Y120.EE2BEG2.EL1END2",
        "INT_L_X0Y120.WL1BEG2.SL1END3",
        "INT_L_X0Y121.SL1BEG3.EL1END3",
        "INT_L_X0Y122.SW6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y122.WL1BEG_N3.SS6END0",
        "INT_L_X0Y123.SS6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y124.EE2BEG2.EL1END2",
        "INT_L_X0Y124.EE2BEG3.SS2END3",
        "INT_L_X0Y124.EL1BEG_N3.LOGIC_OUTS_L18",
        "INT_L_X0Y124.WL1BEG2.SS2END3",
        "INT_L_X0Y125.NR1BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y126.LV_L18.NR1END0",
        "INT_L_X0Y126.NR1BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y126.SS2BEG3.EL1END3",
        "INT_L_X0Y127.NL1BEG2.NL1BEG_N3",
        "INT_L_X0Y127.NL1BEG_N3.NR1END0",
        "INT_L_X0Y127.WL1BEG_N3.LOGIC_OUTS_L18",
        "INT_L_X0Y128.EE2BEG2.NL1END2",
        "INT_L_X0Y128.SS6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y132.EE2BEG2.EL1END2",
        "INT_L_X0Y132.WL1BEG2.WL1END3",
        "INT_L_X0Y137.SW6BEG0.LOGIC_OUTS_L18",
        "INT_L_X0Y17.SS6BEG0.SS6END0",
        "INT_L_X0Y2.IMUX_L34.SS2END1",
        "INT_L_X0Y2.SL1BEG1.SR1END1",
        "INT_L_X0Y23.SS6BEG0.LV_L0",
        "INT_L_X0Y27.LV_L18.LV_L0",
        "INT_L_X0Y3.SR1BEG1.SS6END0",
        "INT_L_X0Y4.SS2BEG1.SR1END1",
        "INT_L_X0Y41.LV_L18.LV_L0",
        "INT_L_X0Y45.LV_L18.LV_L0",
        "INT_L_X0Y5.SR1BEG1.SS6END0",
        "INT_L_X0Y59.LV_L18.LV_L0",
        "INT_L_X0Y63.LV_L18.LV_L0",
        "INT_L_X0Y77.LV_L18.LV_L0",
        "INT_L_X0Y81.LV_L18.LV_L0",
        "INT_L_X0Y9.SS6BEG0.LV_L0",
        "INT_L_X0Y95.LV_L18.LV_L0",
        "INT_L_X0Y96.NN6BEG2.LVB_L0",
        "INT_L_X0Y99.LV_L18.LV_L0",
        "INT_L_X38Y66.SE6BEG0.SE2END0",
        "INT_L_X40Y62.EE4BEG0.SE6END0",
        "INT_L_X42Y51.SE2BEG1.ER1END1",
        "INT_L_X42Y53.SE2BEG1.ER1END1",
        "INT_R_X1Y112.SW6BEG2.LVB0",
        "INT_R_X1Y113.EL1BEG_N3.SE6END0",
        "INT_R_X1Y113.WL1BEG_N3.SE6END0",
        "INT_R_X1Y118.WL1BEG_N3.SE6END0",
        "INT_R_X1Y123.NR1BEG3.EL1END3",
        "INT_R_X1Y124.LVB12.NR1END3",
        "INT_R_X1Y133.EL1BEG_N3.SE6END0",
        "INT_R_X1Y133.WL1BEG_N3.SE6END0",
        "INT_R_X35Y101.LV18.LV0",
        "INT_R_X35Y107.LV18.LV0",
        "INT_R_X35Y111.LV18.LV0",
        "INT_R_X35Y115.LV18.LV0",
        "INT_R_X35Y119.LV18.LV0",
        "INT_R_X35Y125.LV18.LH0",
        "INT_R_X35Y129.LV18.LH0",
        "INT_R_X35Y133.LV18.LH0",
        "INT_R_X35Y137.LV18.LH0",
        "INT_R_X35Y65.SE6BEG0.LV0",
        "INT_R_X35Y71.SE6BEG0.LV0",
        "INT_R_X35Y75.SE6BEG0.LV0",
        "INT_R_X35Y79.SE6BEG0.LV0",
        "INT_R_X35Y83.LV18.LV0",
        "INT_R_X35Y89.LV18.LV0",
        "INT_R_X35Y93.LV18.LV0",
        "INT_R_X35Y97.LV18.LV0",
        "INT_R_X37Y103.LV18.LV0",
        "INT_R_X37Y117.LV18.LH0",
        "INT_R_X37Y121.LV18.LH0",
        "INT_R_X37Y61.SE6BEG0.SE6END0",
        "INT_R_X37Y63.SE6BEG0.LV0",
        "INT_R_X37Y67.SE2BEG0.SE6END0",
        "INT_R_X37Y67.SE6BEG0.LV0",
        "INT_R_X37Y71.SE6BEG0.SE6END0",
        "INT_R_X37Y75.SE6BEG0.SE6END0",
        "INT_R_X37Y81.LV18.LV0",
        "INT_R_X37Y85.LV18.LV0",
        "INT_R_X37Y99.LV18.LV0",
        "INT_R_X39Y51.EE2BEG0.SS6END0",
        "INT_R_X39Y57.SE6BEG0.SE6END0",
        "INT_R_X39Y57.SS6BEG0.SS6END0",
        "INT_R_X39Y59.SE6BEG0.SE6END0",
        "INT_R_X39Y63.SS6BEG0.SE6END0",
        "INT_R_X39Y67.SE6BEG0.SE6END0",
        "INT_R_X39Y71.SE6BEG0.SE6END0",
        "INT_R_X41Y51.ER1BEG1.EE2END0",
        "INT_R_X41Y53.ER1BEG1.SE6END0",
        "INT_R_X41Y55.SE6BEG0.SE6END0",
        "INT_R_X41Y63.SE6BEG0.SE6END0",
        "INT_R_X41Y67.SE6BEG0.SE6END0",
        "INT_R_X43Y50.IMUX34.SE2END1",
        "INT_R_X43Y51.ER1BEG1.SE6END0",
        "INT_R_X43Y51.IMUX34.WR1END1",
        "INT_R_X43Y52.IMUX34.SE2END1",
        "INT_R_X43Y55.IMUX34.SL1END1",
        "INT_R_X43Y56.SL1BEG1.SR1END1",
        "INT_R_X43Y57.SR1BEG1.SS6END0",
        "INT_R_X43Y58.IMUX34.SR1BEG_S0",
        "INT_R_X43Y58.SR1BEG_S0.WL1END3",
        "INT_R_X43Y59.EL1BEG_N3.SE6END0",
        "INT_R_X43Y61.IMUX34.SR1BEG_S0",
        "INT_R_X43Y61.SR1BEG_S0.WW4END_S0_0",
        "INT_R_X43Y63.SS6BEG0.SE6END0",
        "LIOB33_X0Y1.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y1.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y1.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y1.IOB_Y0.SLEW.SLOW",
        "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
        "LIOB33_X0Y121.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y121.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y121.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y121.IOB_Y0.ZINV_D",
        "LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y121.IOB_Y1.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y123.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y123.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y123.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y123.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y123.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y123.IOB_Y0.ZINV_D",
        "LIOB33_X0Y123.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y123.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y123.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y123.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y123.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y123.IOB_Y1.ZINV_D",
        "LIOB33_X0Y125.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y125.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y125.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y125.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y125.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y125.IOB_Y0.ZINV_D",
        "LIOB33_X0Y125.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y125.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y125.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y125.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y125.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y125.IOB_Y1.ZINV_D",
        "LIOB33_X0Y127.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y127.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y127.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y127.IOB_Y0.PULLTYPE.NONE",
        "LIOB33_X0Y127.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y127.IOB_Y0.ZINV_D",
        "LIOB33_X0Y127.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y127.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y127.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y127.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y127.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y127.IOB_Y1.ZINV_D",
        "LIOB33_X0Y137.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y137.IOB_Y0.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y137.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y137.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y137.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y137.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y137.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y137.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y137.IOB_Y1.ZINV_D",
        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
        "RIOB33_SING_X43Y50.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "RIOB33_SING_X43Y50.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_SING_X43Y50.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "RIOB33_SING_X43Y50.IOB_Y0.PULLTYPE.NONE",
        "RIOB33_SING_X43Y50.IOB_Y0.SLEW.SLOW",
        "RIOB33_X43Y51.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "RIOB33_X43Y51.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y51.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "RIOB33_X43Y51.IOB_Y0.PULLTYPE.NONE",
        "RIOB33_X43Y51.IOB_Y0.SLEW.SLOW",
        "RIOB33_X43Y51.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "RIOB33_X43Y51.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y51.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "RIOB33_X43Y51.IOB_Y1.PULLTYPE.NONE",
        "RIOB33_X43Y51.IOB_Y1.SLEW.SLOW",
        "RIOB33_X43Y55.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y55.IOB_Y0.PULLTYPE.PULLDOWN",
        "RIOB33_X43Y55.IOB_Y0.SLEW.FAST",
        "RIOB33_X43Y55.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "RIOB33_X43Y55.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y55.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "RIOB33_X43Y55.IOB_Y1.PULLTYPE.NONE",
        "RIOB33_X43Y55.IOB_Y1.SLEW.SLOW",
        "RIOB33_X43Y57.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "RIOB33_X43Y57.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y57.IOB_Y0.OSERDESE.DATA_RATE_TQ.BUF",
        "RIOB33_X43Y57.IOB_Y0.PULLTYPE.NONE",
        "RIOB33_X43Y57.IOB_Y0.SLEW.SLOW",
        "RIOB33_X43Y57.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y57.IOB_Y1.PULLTYPE.PULLDOWN",
        "RIOB33_X43Y57.IOB_Y1.SLEW.FAST",
        "RIOB33_X43Y61.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y61.IOB_Y0.PULLTYPE.PULLDOWN",
        "RIOB33_X43Y61.IOB_Y0.SLEW.FAST",
        "RIOB33_X43Y61.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "RIOB33_X43Y61.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y61.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "RIOB33_X43Y61.IOB_Y1.PULLTYPE.NONE",
        "RIOB33_X43Y61.IOB_Y1.SLEW.SLOW",
        "RIOB33_X43Y75.IOB_Y0.IN_ONLY",
        "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
        "RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
        "RIOB33_X43Y75.IOB_Y0.ZINV_D",
        "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
        "RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
    ]
}