{
    "info": {
        "GRID_X_MAX": 58,
        "GRID_X_MIN": 10,
        "GRID_Y_MAX": 51,
        "GRID_Y_MIN": 0
    },
    "ports": [
        {
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X60Y130/CLK_HROW_CK_BUFHCLK_L0",
            "pin": "E3",
            "wire": "HCLK_VBRK_X34Y130/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_R_X25Y126/WW2BEG1",
            "pin": "C2",
            "wire": "VBRK_X61Y132/VBRK_WW2END1",
            "wires_outside_roi": [
                "BRAM_INT_INTERFACE_R_X37Y87/INT_INTERFACE_LH6",
                "BRAM_R_X37Y85/BRAM_LH6_2",
                "BRKH_INT_X31Y99/BRKH_INT_LV12",
                "CLBLL_L_X24Y126/CLBLL_WW2END1",
                "CLBLL_L_X26Y123/CLBLL_WW4END3",
                "CLBLL_L_X38Y87/CLBLL_LH6",
                "CLBLL_L_X40Y87/CLBLL_LH4",
                "CLBLL_R_X31Y87/CLBLL_LH12",
                "CLBLM_L_X32Y87/CLBLM_LH12",
                "CLBLM_L_X36Y87/CLBLM_LH8",
                "CLBLM_R_X25Y123/CLBLM_WW4END3",
                "CLBLM_R_X33Y87/CLBLM_LH10",
                "CLBLM_R_X35Y87/CLBLM_LH8",
                "CLBLM_R_X39Y87/CLBLM_LH4",
                "CLBLM_R_X41Y87/CLBLM_LH2",
                "CLK_HROW_TOP_R_X60Y130/CLK_HROW_WW2END1_5",
                "CMT_FIFO_L_X107Y97/CMT_FIFO_LH2_0",
                "CMT_TOP_L_UPPER_T_X106Y96/CMT_TOP_LH2_0",
                "DSP_L_X34Y85/DSP_LH10_2",
                "HCLK_R_X110Y78/HCLK_LV5",
                "HCLK_R_X64Y130/HCLK_NN2BEG2",
                "INT_INTERFACE_L_X34Y87/INT_INTERFACE_LH10",
                "INT_INTERFACE_L_X42Y87/INT_INTERFACE_LH2",
                "INT_INTERFACE_R_X23Y126/INT_INTERFACE_WW2END1",
                "INT_L_X24Y126/WW2A1",
                "INT_L_X26Y123/WW4C3",
                "INT_L_X30Y123/WW4A3",
                "INT_L_X32Y87/LH11",
                "INT_L_X34Y87/LH9",
                "INT_L_X36Y87/LH7",
                "INT_L_X38Y87/LH5",
                "INT_L_X40Y87/LH3",
                "INT_L_X42Y87/LH1",
                "INT_R_X25Y123/NL1BEG2",
                "INT_R_X25Y123/WW4END3",
                "INT_R_X25Y124/NL1END2",
                "INT_R_X25Y124/NN2BEG2",
                "INT_R_X25Y125/NN2A2",
                "INT_R_X25Y126/NN2END2",
                "INT_R_X25Y126/WW2BEG1",
                "INT_R_X27Y123/WW4B3",
                "INT_R_X31Y100/LV13",
                "INT_R_X31Y101/LV14",
                "INT_R_X31Y102/LV15",
                "INT_R_X31Y103/LV16",
                "INT_R_X31Y104/LV17",
                "INT_R_X31Y105/LV0",
                "INT_R_X31Y105/LV18",
                "INT_R_X31Y106/LV1",
                "INT_R_X31Y107/LV2",
                "INT_R_X31Y108/LV3",
                "INT_R_X31Y109/LV4",
                "INT_R_X31Y110/LV5",
                "INT_R_X31Y111/LV6",
                "INT_R_X31Y112/LV7",
                "INT_R_X31Y113/LV8",
                "INT_R_X31Y114/LV9",
                "INT_R_X31Y115/LV10",
                "INT_R_X31Y116/LV11",
                "INT_R_X31Y117/LV12",
                "INT_R_X31Y118/LV13",
                "INT_R_X31Y119/LV14",
                "INT_R_X31Y120/LV15",
                "INT_R_X31Y121/LV16",
                "INT_R_X31Y122/LV17",
                "INT_R_X31Y123/LV18",
                "INT_R_X31Y123/WW4BEG3",
                "INT_R_X31Y87/LH12",
                "INT_R_X31Y87/LV0",
                "INT_R_X31Y88/LV1",
                "INT_R_X31Y89/LV2",
                "INT_R_X31Y90/LV3",
                "INT_R_X31Y91/LV4",
                "INT_R_X31Y92/LV5",
                "INT_R_X31Y93/LV6",
                "INT_R_X31Y94/LV7",
                "INT_R_X31Y95/LV8",
                "INT_R_X31Y96/LV9",
                "INT_R_X31Y97/LV10",
                "INT_R_X31Y98/LV11",
                "INT_R_X31Y99/LV12",
                "INT_R_X33Y87/LH10",
                "INT_R_X35Y87/LH8",
                "INT_R_X37Y87/LH6",
                "INT_R_X39Y87/LH4",
                "INT_R_X41Y87/LH2",
                "INT_R_X43Y68/LOGIC_OUTS18",
                "INT_R_X43Y68/NR1BEG0",
                "INT_R_X43Y69/LV0",
                "INT_R_X43Y69/NR1END0",
                "INT_R_X43Y70/LV1",
                "INT_R_X43Y71/LV2",
                "INT_R_X43Y72/LV3",
                "INT_R_X43Y73/LV4",
                "INT_R_X43Y74/LV5",
                "INT_R_X43Y75/LV6",
                "INT_R_X43Y76/LV7",
                "INT_R_X43Y77/LV8",
                "INT_R_X43Y78/LV9",
                "INT_R_X43Y79/LV10",
                "INT_R_X43Y80/LV11",
                "INT_R_X43Y81/LV12",
                "INT_R_X43Y82/LV13",
                "INT_R_X43Y83/LV14",
                "INT_R_X43Y84/LV15",
                "INT_R_X43Y85/LV16",
                "INT_R_X43Y86/LV17",
                "INT_R_X43Y87/LH0",
                "INT_R_X43Y87/LV18",
                "IO_INT_INTERFACE_R_X43Y68/INT_INTERFACE_LOGIC_OUTS18",
                "IO_INT_INTERFACE_R_X43Y68/INT_INTERFACE_LOGIC_OUTS_B18",
                "PCIE_INT_INTERFACE_L_X30Y123/INT_INTERFACE_WW4B3",
                "PCIE_INT_INTERFACE_R_X27Y123/INT_INTERFACE_WW4B3",
                "PCIE_TOP_X71Y125/PCIE_WW4B3_3",
                "RIOB33_X43Y67/IOB_IBUF0",
                "RIOI3_X43Y67/IOI_ILOGIC0_O",
                "RIOI3_X43Y67/IOI_LOGIC_OUTS18_1",
                "RIOI3_X43Y67/RIOI_I0",
                "RIOI3_X43Y67/RIOI_IBUF0",
                "RIOI3_X43Y67/RIOI_ILOGIC0_D",
                "R_TERM_INT_X112Y71/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X105Y91/VBRK_LH2",
                "VBRK_X61Y132/VBRK_WW2END1",
                "VBRK_X66Y128/VBRK_WW4END3",
                "VBRK_X80Y91/VBRK_LH12",
                "VBRK_X85Y91/VBRK_LH10",
                "VBRK_X96Y91/VBRK_LH6"
            ]
        },
        {
            "name": "din[1]",
            "node": "INT_L_X0Y102/EE2BEG2",
            "pin": "A9",
            "wire": "VBRK_X9Y107/VBRK_EE2A2",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y112/CMT_FIFO_EE2A2_1",
                "CMT_TOP_R_LOWER_B_X8Y113/CMT_TOP_EE2A2_2",
                "INT_INTERFACE_R_X1Y102/INT_INTERFACE_EE2A2",
                "INT_L_X0Y102/EE2BEG2",
                "INT_L_X0Y102/SE2END2",
                "INT_L_X0Y102/SW2A2",
                "INT_L_X0Y103/SE6END2",
                "INT_L_X0Y103/SW2BEG2",
                "INT_L_X0Y103/SW6E2",
                "INT_L_X0Y104/SW6D2",
                "INT_L_X0Y105/SW6C2",
                "INT_L_X0Y106/SW6B2",
                "INT_L_X0Y107/SW6A2",
                "INT_L_X0Y119/SE2A3",
                "INT_L_X0Y120/EL1END3",
                "INT_L_X0Y120/SE2BEG3",
                "INT_L_X0Y120/WL1BEG3",
                "INT_L_X0Y121/LOGIC_OUTS_L18",
                "INT_L_X0Y121/WL1BEG_N3",
                "INT_R_X1Y102/EE2A2",
                "INT_R_X1Y107/LVB0",
                "INT_R_X1Y107/SW6BEG2",
                "INT_R_X1Y108/LVB1",
                "INT_R_X1Y109/LVB2",
                "INT_R_X1Y110/LVB3",
                "INT_R_X1Y111/LVB4",
                "INT_R_X1Y112/LVB5",
                "INT_R_X1Y113/LVB6",
                "INT_R_X1Y114/LVB7",
                "INT_R_X1Y115/LVB8",
                "INT_R_X1Y116/LVB9",
                "INT_R_X1Y117/LVB10",
                "INT_R_X1Y118/LVB11",
                "INT_R_X1Y119/LVB12",
                "INT_R_X1Y119/SE2END3",
                "IO_INT_INTERFACE_L_X0Y102/INT_INTERFACE_SE2A2",
                "IO_INT_INTERFACE_L_X0Y102/INT_INTERFACE_SW2A2",
                "IO_INT_INTERFACE_L_X0Y103/INT_INTERFACE_SE4C2",
                "IO_INT_INTERFACE_L_X0Y103/INT_INTERFACE_SW4END2",
                "IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_EL1BEG3",
                "IO_INT_INTERFACE_L_X0Y120/INT_INTERFACE_WL1END3",
                "IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_LOGIC_OUTS_L18",
                "IO_INT_INTERFACE_L_X0Y121/INT_INTERFACE_LOGIC_OUTS_L_B18",
                "LIOB33_X0Y121/IOB_IBUF1",
                "LIOI3_X0Y121/IOI_ILOGIC1_O",
                "LIOI3_X0Y121/IOI_LOGIC_OUTS18_0",
                "LIOI3_X0Y121/LIOI_I1",
                "LIOI3_X0Y121/LIOI_IBUF1",
                "LIOI3_X0Y121/LIOI_ILOGIC1_D",
                "L_TERM_INT_X2Y107/L_TERM_INT_SW2BEG2",
                "L_TERM_INT_X2Y108/L_TERM_INT_SW4C2",
                "L_TERM_INT_X2Y125/L_TERM_INT_WR1BEG2",
                "L_TERM_INT_X2Y126/TERM_INT_LOGIC_OUTS_L_B18",
                "VBRK_X9Y107/VBRK_EE2A2"
            ]
        },
        {
            "name": "dout[0]",
            "node": "INT_L_X2Y145/SW6BEG0",
            "pin": "T10",
            "wire": "VBRK_X9Y151/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_8",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_8",
                "INT_INTERFACE_R_X1Y145/INT_INTERFACE_SW4A0",
                "INT_L_X0Y141/SW6END0",
                "INT_R_X1Y141/SW6E0",
                "INT_R_X1Y142/SW6D0",
                "INT_R_X1Y143/SW6C0",
                "INT_R_X1Y144/SW6B0",
                "INT_R_X1Y145/SW6A0",
                "VBRK_X9Y151/VBRK_SW4A0"
            ]
        },
        {
            "name": "dout[1]",
            "node": "INT_L_X2Y147/SW6BEG0",
            "pin": "D10",
            "wire": "VBRK_X9Y153/VBRK_SW4A0",
            "wires_outside_roi": [
                "CMT_FIFO_R_X7Y149/CMT_FIFO_SW4A0_10",
                "CMT_TOP_R_UPPER_T_X8Y148/CMT_TOP_SW4A0_10",
                "INT_INTERFACE_R_X1Y147/INT_INTERFACE_SW4A0",
                "INT_L_X0Y143/SW6END0",
                "INT_R_X1Y143/SW6E0",
                "INT_R_X1Y144/SW6D0",
                "INT_R_X1Y145/SW6C0",
                "INT_R_X1Y146/SW6B0",
                "INT_R_X1Y147/SW6A0",
                "VBRK_X9Y153/VBRK_SW4A0"
            ]
        }
    ],
    "required_features": [
        "",
        "CLK_BUFG_REBUF_X60Y117.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
        "CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y117.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y142.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y38.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y65.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
        "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y65.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_REBUF_X60Y90.CLK_BUFG_REBUF_R_CK_GCLK16_TOP.CLK_BUFG_REBUF_R_CK_GCLK16_BOT",
        "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_ABOVE",
        "CLK_BUFG_REBUF_X60Y90.GCLK16_ENABLE_BELOW",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IN_USE",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.IS_IGNORE1_INVERTED",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_CE0",
        "CLK_BUFG_TOP_R_X60Y53.BUFGCTRL.BUFGCTRL_X0Y0.ZINV_S0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I0.CLK_BUFG_TOP_R_CK_MUXED0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL0_I1.CLK_BUFG_IMUX28_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I0.CLK_BUFG_IMUX30_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL10_I1.CLK_BUFG_IMUX30_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I0.CLK_BUFG_IMUX31_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL11_I1.CLK_BUFG_IMUX31_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I0.CLK_BUFG_IMUX28_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL12_I1.CLK_BUFG_IMUX28_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I0.CLK_BUFG_IMUX29_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL13_I1.CLK_BUFG_IMUX29_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I0.CLK_BUFG_IMUX30_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL14_I1.CLK_BUFG_IMUX30_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I0.CLK_BUFG_IMUX31_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL15_I1.CLK_BUFG_IMUX31_3",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I0.CLK_BUFG_IMUX29_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL1_I1.CLK_BUFG_IMUX29_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I0.CLK_BUFG_IMUX30_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL2_I1.CLK_BUFG_IMUX30_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I0.CLK_BUFG_IMUX31_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL3_I1.CLK_BUFG_IMUX31_0",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I0.CLK_BUFG_IMUX28_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL4_I1.CLK_BUFG_IMUX28_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I0.CLK_BUFG_IMUX29_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL5_I1.CLK_BUFG_IMUX29_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I0.CLK_BUFG_IMUX30_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL6_I1.CLK_BUFG_IMUX30_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I0.CLK_BUFG_IMUX31_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL7_I1.CLK_BUFG_IMUX31_1",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I0.CLK_BUFG_IMUX28_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL8_I1.CLK_BUFG_IMUX28_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I0.CLK_BUFG_IMUX29_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_BUFGCTRL9_I1.CLK_BUFG_IMUX29_2",
        "CLK_BUFG_TOP_R_X60Y53.CLK_BUFG_CK_GCLK16.CLK_BUFG_BUFGCTRL0_O",
        "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.IN_USE",
        "CLK_HROW_TOP_R_X60Y130.BUFHCE.BUFHCE_X0Y0.ZINV_CE",
        "CLK_HROW_TOP_R_X60Y130.CLK_HROW_CK_MUX_OUT_L0.CLK_HROW_R_CK_GCLK16",
        "CLK_HROW_TOP_R_X60Y130.CLK_HROW_R_CK_GCLK16_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_CK_IN_R0_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_R_CK_GCLK16_ACTIVE",
        "CLK_HROW_TOP_R_X60Y78.CLK_HROW_TOP_R_CK_BUFG_CASCO0.CLK_HROW_CK_IN_R0",
        "HCLK_CMT_L_X106Y78.HCLK_CMT_CCIO0_ACTIVE",
        "HCLK_CMT_L_X106Y78.HCLK_CMT_CK_IN0.HCLK_CMT_CCIO0",
        "HCLK_CMT_X8Y130.HCLK_CMT_CK_BUFHCLK0_ACTIVE",
        "INT_L_X0Y1.IMUX_L34.SL1END1",
        "INT_L_X0Y102.EE2BEG2.SE2END2",
        "INT_L_X0Y103.SW2BEG2.SE6END2",
        "INT_L_X0Y105.LV_L18.LV_L0",
        "INT_L_X0Y111.IMUX_L34.SL1END1",
        "INT_L_X0Y112.SL1BEG1.SR1END1",
        "INT_L_X0Y113.SR1BEG1.SS6END0",
        "INT_L_X0Y119.SS6BEG0.SS6END0",
        "INT_L_X0Y120.SE2BEG3.EL1END3",
        "INT_L_X0Y121.WL1BEG_N3.LOGIC_OUTS_L18",
        "INT_L_X0Y123.LV_L18.LV_L0",
        "INT_L_X0Y125.SS6BEG0.LV_L0",
        "INT_L_X0Y141.LV_L18.SW6END0",
        "INT_L_X0Y143.LV_L18.SW6END0",
        "INT_L_X0Y15.SS6BEG0.LV_L0",
        "INT_L_X0Y2.SL1BEG1.SR1END1",
        "INT_L_X0Y3.SR1BEG1.SS6END0",
        "INT_L_X0Y33.LV_L18.LV_L0",
        "INT_L_X0Y51.LV_L18.LV_L0",
        "INT_L_X0Y69.LV_L18.LV_L0",
        "INT_L_X0Y87.LV_L18.LV_L0",
        "INT_L_X0Y9.SS6BEG0.SS6END0",
        "INT_R_X1Y107.SW6BEG2.LVB0",
        "INT_R_X1Y119.LVB12.SE2END3",
        "INT_R_X25Y123.NL1BEG2.WW4END3",
        "INT_R_X25Y124.NN2BEG2.NL1END2",
        "INT_R_X25Y126.WW2BEG1.NN2END2",
        "INT_R_X31Y105.LV0.LV18",
        "INT_R_X31Y123.WW4BEG3.LV18",
        "INT_R_X31Y87.LV0.LH12",
        "INT_R_X43Y68.NR1BEG0.LOGIC_OUTS18",
        "INT_R_X43Y69.LV0.NR1END0",
        "INT_R_X43Y87.LH0.LV18",
        "LIOB33_X0Y1.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y1.IOB_Y0.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y1.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y1.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y1.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y1.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y1.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y1.IOB_Y1.SLEW.SLOW",
        "LIOB33_X0Y111.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y111.IOB_Y0.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y111.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y111.IOB_Y1.LVCMOS33_LVTTL.DRIVE.I12_I16",
        "LIOB33_X0Y111.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y111.IOB_Y1.OSERDESE.DATA_RATE_TQ.BUF",
        "LIOB33_X0Y111.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y111.IOB_Y1.SLEW.SLOW",
        "LIOB33_X0Y121.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y121.IOB_Y0.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y121.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y121.IOB_Y1.IN_ONLY",
        "LIOB33_X0Y121.IOB_Y1.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y121.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y121.IOB_Y1.PULLTYPE.NONE",
        "LIOB33_X0Y121.IOB_Y1.SLEW.FAST",
        "LIOB33_X0Y121.IOB_Y1.ZINV_D",
        "LIOB33_X0Y43.IOB_Y0.IN_ONLY",
        "LIOB33_X0Y43.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "LIOB33_X0Y43.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y43.IOB_Y0.PULLTYPE.PULLUP",
        "LIOB33_X0Y43.IOB_Y0.SLEW.FAST",
        "LIOB33_X0Y43.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "LIOB33_X0Y43.IOB_Y1.PULLTYPE.PULLDOWN",
        "LIOB33_X0Y43.IOB_Y1.SLEW.FAST",
        "RIOB33_X43Y67.IOB_Y0.IN_ONLY",
        "RIOB33_X43Y67.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "RIOB33_X43Y67.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y67.IOB_Y0.PULLTYPE.NONE",
        "RIOB33_X43Y67.IOB_Y0.SLEW.FAST",
        "RIOB33_X43Y67.IOB_Y0.ZINV_D",
        "RIOB33_X43Y67.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y67.IOB_Y1.PULLTYPE.PULLDOWN",
        "RIOB33_X43Y67.IOB_Y1.SLEW.FAST",
        "RIOB33_X43Y75.IOB_Y0.IN_ONLY",
        "RIOB33_X43Y75.IOB_Y0.LVCMOS25_LVCMOS33_LVTTL.IN",
        "RIOB33_X43Y75.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y75.IOB_Y0.PULLTYPE.NONE",
        "RIOB33_X43Y75.IOB_Y0.SLEW.FAST",
        "RIOB33_X43Y75.IOB_Y0.ZINV_D",
        "RIOB33_X43Y75.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE",
        "RIOB33_X43Y75.IOB_Y1.PULLTYPE.PULLDOWN",
        "RIOB33_X43Y75.IOB_Y1.SLEW.FAST"
    ]
}