{
    "info": {
        "GRID_X_MAX": 118,
        "GRID_X_MIN": 83,
        "GRID_Y_MAX": 51,
        "GRID_Y_MIN": 0
    },
    "ports": [
        {
            "name": "clk",
            "node": "CLK_HROW_TOP_R_X82Y78/CLK_HROW_CK_BUFHCLK_R0",
            "pin": "K17",
            "wire": "HCLK_VBRK_X83Y78/HCLK_VBRK_CK_BUFHCLK0"
        },
        {
            "name": "din[0]",
            "node": "INT_R_X31Y53/WW2BEG1",
            "pin": "J15",
            "wire": "VBRK_X118Y56/VBRK_WW2END1",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_2",
                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_3",
                "INT_INTERFACE_L_X30Y53/INT_INTERFACE_WW2END1",
                "INT_L_X30Y50/NE6BEG1",
                "INT_L_X30Y50/WW2END0",
                "INT_L_X30Y53/WW2A1",
                "INT_R_X31Y50/EE2BEG0",
                "INT_R_X31Y50/LOGIC_OUTS18",
                "INT_R_X31Y50/NE6A1",
                "INT_R_X31Y50/WW2A0",
                "INT_R_X31Y51/NE6B1",
                "INT_R_X31Y52/NE6C1",
                "INT_R_X31Y53/NE6D1",
                "INT_R_X31Y53/SR1END1",
                "INT_R_X31Y53/WW2BEG1",
                "INT_R_X31Y54/NE6E1",
                "INT_R_X31Y54/NW6END1",
                "INT_R_X31Y54/SR1BEG1",
                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_EE2BEG0",
                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_LOGIC_OUTS18",
                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_LOGIC_OUTS_B18",
                "IO_INT_INTERFACE_R_X31Y50/INT_INTERFACE_WW2A0",
                "IO_INT_INTERFACE_R_X31Y54/INT_INTERFACE_NE4C1",
                "IO_INT_INTERFACE_R_X31Y54/INT_INTERFACE_NW4END1",
                "RIOB33_SING_X31Y50/IOB_IBUF0",
                "RIOI3_SING_X31Y50/IOI_ILOGIC0_O",
                "RIOI3_SING_X31Y50/IOI_LOGIC_OUTS18_0",
                "RIOI3_SING_X31Y50/RIOI_I0",
                "RIOI3_SING_X31Y50/RIOI_IBUF0",
                "RIOI3_SING_X31Y50/RIOI_ILOGIC0_D",
                "R_TERM_INT_X125Y53/R_TERM_INT_WW2A0",
                "R_TERM_INT_X125Y53/TERM_INT_LOGIC_OUTS_L_B18",
                "R_TERM_INT_X125Y57/R_TERM_INT_NW4END1"
            ]
        },
        {
            "name": "din[1]",
            "node": "INT_R_X31Y56/WW2BEG1",
            "pin": "G15",
            "wire": "VBRK_X118Y59/VBRK_WW2END1",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_5",
                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_6",
                "INT_INTERFACE_L_X30Y56/INT_INTERFACE_WW2END1",
                "INT_L_X30Y56/WW2A1",
                "INT_L_X30Y57/ER1BEG1",
                "INT_L_X30Y57/SW6END0",
                "INT_R_X31Y56/SL1END1",
                "INT_R_X31Y56/WW2BEG1",
                "INT_R_X31Y57/ER1END1",
                "INT_R_X31Y57/SL1BEG1",
                "INT_R_X31Y57/SW6E0",
                "INT_R_X31Y58/SW6D0",
                "INT_R_X31Y59/SW6C0",
                "INT_R_X31Y60/SW6B0",
                "INT_R_X31Y61/LOGIC_OUTS18",
                "INT_R_X31Y61/SE6BEG0",
                "INT_R_X31Y61/SW6A0",
                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_LOGIC_OUTS18",
                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_LOGIC_OUTS_B18",
                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_SE4BEG0",
                "IO_INT_INTERFACE_R_X31Y61/INT_INTERFACE_SW4A0",
                "RIOB33_X31Y61/IOB_IBUF1",
                "RIOI3_X31Y61/IOI_ILOGIC1_O",
                "RIOI3_X31Y61/IOI_LOGIC_OUTS18_0",
                "RIOI3_X31Y61/RIOI_I1",
                "RIOI3_X31Y61/RIOI_IBUF1",
                "RIOI3_X31Y61/RIOI_ILOGIC1_D",
                "R_TERM_INT_X125Y64/R_TERM_INT_SW4A0",
                "R_TERM_INT_X125Y64/TERM_INT_LOGIC_OUTS_L_B18"
            ]
        },
        {
            "name": "din[2]",
            "node": "INT_R_X31Y59/WW2BEG1",
            "pin": "K18",
            "wire": "VBRK_X118Y62/VBRK_WW2END1",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_8",
                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_9",
                "HCLK_R_X123Y78/HCLK_LV16",
                "INT_INTERFACE_L_X30Y59/INT_INTERFACE_WW2END1",
                "INT_L_X30Y59/WW2A1",
                "INT_R_X31Y58/LV0",
                "INT_R_X31Y59/LV1",
                "INT_R_X31Y59/SS2END1",
                "INT_R_X31Y59/WW2BEG1",
                "INT_R_X31Y60/LV2",
                "INT_R_X31Y60/SS2A1",
                "INT_R_X31Y61/LV3",
                "INT_R_X31Y61/SS2BEG1",
                "INT_R_X31Y61/SS6END1",
                "INT_R_X31Y62/LV4",
                "INT_R_X31Y62/SS6E1",
                "INT_R_X31Y63/LV5",
                "INT_R_X31Y63/SS6D1",
                "INT_R_X31Y64/LV6",
                "INT_R_X31Y64/SS6C1",
                "INT_R_X31Y65/LV7",
                "INT_R_X31Y65/SS6B1",
                "INT_R_X31Y66/LV8",
                "INT_R_X31Y66/SS6A1",
                "INT_R_X31Y67/LV9",
                "INT_R_X31Y67/SS6BEG1",
                "INT_R_X31Y68/LV10",
                "INT_R_X31Y69/LV11",
                "INT_R_X31Y70/LV12",
                "INT_R_X31Y71/LV13",
                "INT_R_X31Y72/LV14",
                "INT_R_X31Y73/LV15",
                "INT_R_X31Y74/LV16",
                "INT_R_X31Y75/LOGIC_OUTS18",
                "INT_R_X31Y75/LV17",
                "INT_R_X31Y75/NR1BEG0",
                "INT_R_X31Y76/LV18",
                "INT_R_X31Y76/NR1END0",
                "IO_INT_INTERFACE_R_X31Y75/INT_INTERFACE_LOGIC_OUTS18",
                "IO_INT_INTERFACE_R_X31Y75/INT_INTERFACE_LOGIC_OUTS_B18",
                "RIOB33_X31Y75/IOB_IBUF1",
                "RIOI3_X31Y75/IOI_ILOGIC1_O",
                "RIOI3_X31Y75/IOI_LOGIC_OUTS18_0",
                "RIOI3_X31Y75/RIOI_I1",
                "RIOI3_X31Y75/RIOI_IBUF1",
                "RIOI3_X31Y75/RIOI_ILOGIC1_D",
                "R_TERM_INT_X125Y79/TERM_INT_LOGIC_OUTS_L_B18"
            ]
        },
        {
            "name": "din[3]",
            "node": "INT_R_X31Y62/WW2BEG1",
            "pin": "K19",
            "wire": "VBRK_X118Y65/VBRK_WW2END1",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y60/CMT_FIFO_WW2END1_11",
                "CMT_TOP_L_LOWER_B_X119Y61/CMT_TOP_WW2END1_12",
                "HCLK_L_X122Y78/HCLK_LV16",
                "INT_INTERFACE_L_X30Y62/INT_INTERFACE_WW2END1",
                "INT_L_X30Y58/LV_L0",
                "INT_L_X30Y59/LV_L1",
                "INT_L_X30Y60/LV_L2",
                "INT_L_X30Y61/LV_L3",
                "INT_L_X30Y62/LV_L4",
                "INT_L_X30Y62/WW2A1",
                "INT_L_X30Y63/LV_L5",
                "INT_L_X30Y64/LV_L6",
                "INT_L_X30Y65/LV_L7",
                "INT_L_X30Y66/LV_L8",
                "INT_L_X30Y67/LV_L9",
                "INT_L_X30Y67/SE6BEG1",
                "INT_L_X30Y68/LV_L10",
                "INT_L_X30Y69/LV_L11",
                "INT_L_X30Y70/LV_L12",
                "INT_L_X30Y71/LV_L13",
                "INT_L_X30Y72/LV_L14",
                "INT_L_X30Y73/LV_L15",
                "INT_L_X30Y74/LV_L16",
                "INT_L_X30Y75/LV_L17",
                "INT_L_X30Y76/LV_L18",
                "INT_L_X30Y76/SW6END0",
                "INT_R_X31Y62/SL1END1",
                "INT_R_X31Y62/WW2BEG1",
                "INT_R_X31Y63/SE6E1",
                "INT_R_X31Y63/SL1BEG1",
                "INT_R_X31Y63/SW6END1",
                "INT_R_X31Y64/SE6D1",
                "INT_R_X31Y65/SE6C1",
                "INT_R_X31Y66/SE6B1",
                "INT_R_X31Y67/SE6A1",
                "INT_R_X31Y76/SW6E0",
                "INT_R_X31Y77/SW6D0",
                "INT_R_X31Y78/SW6C0",
                "INT_R_X31Y79/SW6B0",
                "INT_R_X31Y80/LOGIC_OUTS18",
                "INT_R_X31Y80/SE6BEG0",
                "INT_R_X31Y80/SW6A0",
                "IO_INT_INTERFACE_R_X31Y63/INT_INTERFACE_SE4C1",
                "IO_INT_INTERFACE_R_X31Y63/INT_INTERFACE_SW4END1",
                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_LOGIC_OUTS18",
                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_LOGIC_OUTS_B18",
                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_SE4BEG0",
                "IO_INT_INTERFACE_R_X31Y80/INT_INTERFACE_SW4A0",
                "RIOB33_X31Y79/IOB_IBUF0",
                "RIOI3_X31Y79/IOI_ILOGIC0_O",
                "RIOI3_X31Y79/IOI_LOGIC_OUTS18_1",
                "RIOI3_X31Y79/RIOI_I0",
                "RIOI3_X31Y79/RIOI_IBUF0",
                "RIOI3_X31Y79/RIOI_ILOGIC0_D",
                "R_TERM_INT_X125Y66/R_TERM_INT_SW4END1",
                "R_TERM_INT_X125Y84/R_TERM_INT_SW4A0",
                "R_TERM_INT_X125Y84/TERM_INT_LOGIC_OUTS_L_B18"
            ]
        },
        {
            "name": "dout[0]",
            "node": "INT_R_X29Y81/EE2BEG0",
            "pin": "H15",
            "wire": "VBRK_X118Y85/VBRK_EE2BEG0",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y85/CMT_FIFO_EE2BEG0_6",
                "CMT_TOP_L_UPPER_B_X119Y83/CMT_TOP_EE2BEG0_6",
                "INT_INTERFACE_L_X30Y81/INT_INTERFACE_EE2BEG0",
                "INT_L_X30Y81/EE2A0",
                "INT_R_X31Y81/EE2END0"
            ]
        },
        {
            "name": "dout[1]",
            "node": "INT_R_X29Y84/EE2BEG0",
            "pin": "E17",
            "wire": "VBRK_X118Y88/VBRK_EE2BEG0",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y85/CMT_FIFO_EE2BEG0_9",
                "CMT_TOP_L_UPPER_B_X119Y83/CMT_TOP_EE2BEG0_9",
                "INT_INTERFACE_L_X30Y84/INT_INTERFACE_EE2BEG0",
                "INT_L_X30Y84/EE2A0",
                "INT_R_X31Y84/EE2END0"
            ]
        },
        {
            "name": "dout[2]",
            "node": "INT_R_X29Y87/EE2BEG0",
            "pin": "M14",
            "wire": "VBRK_X118Y91/VBRK_EE2BEG0",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_0",
                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_0",
                "INT_INTERFACE_L_X30Y87/INT_INTERFACE_EE2BEG0",
                "INT_L_X30Y87/EE2A0",
                "INT_R_X31Y87/EE2END0"
            ]
        },
        {
            "name": "dout[3]",
            "node": "INT_R_X29Y90/EE2BEG0",
            "pin": "M15",
            "wire": "VBRK_X118Y94/VBRK_EE2BEG0",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_3",
                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_3",
                "INT_INTERFACE_L_X30Y90/INT_INTERFACE_EE2BEG0",
                "INT_L_X30Y90/EE2A0",
                "INT_R_X31Y90/EE2END0"
            ]
        },
        {
            "name": "dout[4]",
            "node": "INT_R_X29Y93/EE2BEG0",
            "pin": "D18",
            "wire": "VBRK_X118Y97/VBRK_EE2BEG0",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_6",
                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_6",
                "INT_INTERFACE_L_X30Y93/INT_INTERFACE_EE2BEG0",
                "INT_L_X30Y93/EE2A0",
                "INT_R_X31Y93/EE2END0"
            ]
        },
        {
            "name": "dout[5]",
            "node": "INT_R_X29Y96/EE2BEG0",
            "pin": "G14",
            "wire": "VBRK_X118Y100/VBRK_EE2BEG0",
            "wires_outside_roi": [
                "CMT_FIFO_L_X120Y97/CMT_FIFO_EE2BEG0_9",
                "CMT_TOP_L_UPPER_T_X119Y96/CMT_TOP_EE2BEG0_9",
                "INT_INTERFACE_L_X30Y96/INT_INTERFACE_EE2BEG0",
                "INT_L_X30Y96/EE2A0",
                "INT_R_X31Y96/EE2END0"
            ]
        }
    ],
    "required_features": [
        "",
        ""
    ]
}