)]}'
{
  "id": "6ed8c8fcdf8d5fea80f1b8815ff80227bc1f341b",
  "repo": "prjxray",
  "revision": "11ce55d4aa61c2ab3799ea42a8d6fe4dcbbac880",
  "path": "minitests/litex/min/arty/verilog/VexRiscv_Lite.v"
}