Google Git
Sign in
foss-fpga-tools / prjxray / 13b7d2b517ee5c6adb57024d17a62a5ed2dbfe38 / . / minitests / litex_litedram / src.yosys
tree: 6b289b973dd9b08a3c872867f3180980a5ae2cb6 [path history] [tgz]
  1. verilog/
  2. ExtractFrames.py
  3. Makefile
  4. mem.init
  5. mem_1.init
  6. synth.ys
  7. top.tcl
  8. top.xdc