tree: e873dac9f2bf38d3ef481ceec0aa5be1b8dd18fb [path history] [tgz]
  1. .gitignore
  2. generate.py
  3. generate.sh
  4. generate.tcl
  5. Makefile
  6. README.md
  7. top.py
fuzzers/018-clbram/README.md

CLBRAM Fuzzer

Purpose

Solves SLICEM specific bits:
-Shift register LUT (SRL)
-Memory size
-RAM vs LUT
-Related muxes

Algorithm

Outcome

CLB.SLICE_X0.ALUT.RAM 31_16
CLB.SLICE_X0.ALUT.SMALL 00_04
CLB.SLICE_X0.ALUT.SRL 30_16
CLB.SLICE_X0.BLUT.RAM 31_17
CLB.SLICE_X0.BLUT.SMALL 00_24
CLB.SLICE_X0.BLUT.SRL 30_17
CLB.SLICE_X0.CLUT.RAM 31_46
CLB.SLICE_X0.CLUT.SMALL 00_28
CLB.SLICE_X0.CLUT.SRL 30_46
CLB.SLICE_X0.DLUT.RAM 31_47
CLB.SLICE_X0.DLUT.SMALL 01_59
CLB.SLICE_X0.DLUT.SRL 30_47
CLB.SLICE_X0.WA7USED 00_40
CLB.SLICE_X0.WA8USED 01_27
CLB.SLICE_X0.WEMUX.CE 01_23