Google Git
Sign in
foss-fpga-tools/prjxray/2fcd3f9b8dc407151655754951e08f48bde6d88b/./minitests/litex/min/arty/src.yosys
tree: db3a072a5b206ca0966d38885a6603a11d4b2aa8 [path history] [tgz]
  1. mem.init ⇨ ../verilog/mem.init
  2. mem_1.init ⇨ ../verilog/mem_1.init
  3. mem_2.init ⇨ ../verilog/mem_2.init
  4. Makefile
  5. synth.ys
  6. top.tcl
  7. top.xdc