)]}'
{
  "id": "84007bb9cba7c16106272463ae99857bf26949c0",
  "repo": "prjxray",
  "revision": "30e6899bdb3b9b910248127a9fbbc2f22042be56",
  "path": "minitests/litex/min/arty/verilog/top.v"
}