)]}'
{
  "id": "d5e10db0b60bf3b1d8f585abc697f0feac3dacf0",
  "repo": "prjxray",
  "revision": "326576604b8c011f67d68b8b3c427ba4d45783a2",
  "path": "minitests/litex/min_ddr/arty/verilog/mem.init"
}