)]}'
{
  "id": "edeb125a0fab91da81af802e9f83f9d736b72fd9",
  "repo": "prjxray",
  "revision": "3bbb46bbf3df6f4d3a813028758c0261082db7ee",
  "path": "minitests/litex/min/arty/verilog/mem.init"
}