)]}'
{
  "id": "6ed8c8fcdf8d5fea80f1b8815ff80227bc1f341b",
  "repo": "prjxray",
  "revision": "4aed806db67697a9fb4c7e5f35eaaacdf5b8e6fa",
  "path": "minitests/litex/min_ddr/arty/verilog/VexRiscv_Lite.v"
}