)]}'
{
  "id": "bf52ef90bfda3ac9aecf382d463930a52b95b01c",
  "repo": "prjxray",
  "revision": "4dd4533912c5240e2ab46c28a0a24be3bdb5ceeb",
  "path": "minitests/litex/min_ddr/arty/verilog/top.v"
}