tree: a61d7368c725c5a6854a1dd8d973e608bb01d077 [path history] [tgz]
  1. tcl/
  2. .gitignore
  3. Makefile
  4. README.md
  5. requirements.txt
  6. retarget.v
minitests/litex/nexys_video_sata/README.md

LiteSATA minitest

This minitest is intended to provide a counter-prove on the possible remaining features to document for the Gigabit Transcievers (GTP tiles).

It uses the following litex modules:

Repo URLSHA
https://github.com/enjoy-digital/litex7abfbd9
https://github.com/enjoy-digital/litedramab2423e
https://github.com/enjoy-digital/liteeth7448170
https://github.com/enjoy-digital/liteiclink0980a7c
https://github.com/enjoy-digital/litesatafae9f8d
https://github.com/enjoy-digital/litex-boards1d8f0a9
https://github.com/m-labs/migen40b1092
https://github.com/nmigen/nmigen490fca5
https://github.com/litex-hub/pythondata-cpu-vexriscv16c5dde

The minitest synthesis step can be performed with Yosys or Vivado.

The final FASM file with the unknown bits can be obtained by running the following:

make all

All the pre-requisites (LiteX, Yosys, etc.) are automatically installed/built. It is required though to have Vivado installed in the system.