tree: 0d968df807985590b3cb6e92186f908965419150 [path history] [tgz]
  1. minitest/
  2. generate.py
  3. generate.sh
  4. generate.tcl
  5. Makefile
  6. README.md
  7. top.py
fuzzers/018-clb-ram/README.md

clb-ram Fuzzer

PrimitiveRAMSMALLSRL
LUT6
SRL16EXX
SRLC32EX
RAM32X1SXX
RAM64X1SX
RAM32MXX
RAM32X1DXX
RAM64MX
RAM64X1DX
RAM128X1DX
RAM256X1SX
RAM128X1SX

NLUT.RAM

Set to make a RAM* family primitive, otherwise is a SRL or LUT function generator.

NLUT.SMALL

Seems to be set on smaller primitives.

NLUT.SRL

Whether to make a shift register LUT (SRL). Set when using SRL16E or SRLC32E

WA7USED

Set to 1 to propagate CLB's CX input to WA7

WA8USED

Set to 1 to propagate CLB's BX input to WA8

WEMUX.CE

WEMUX.CECLB RAM write enable
0CLB WE input
1CLB CE input