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foss-fpga-tools / prjxray / 645b8a9b8e7157d5ad0e2d6dc961b3bff0e847d5 / . / minitests / litex_litedram / src.yosys
tree: 6b289b973dd9b08a3c872867f3180980a5ae2cb6 [path history] [tgz]
  1. verilog/
  2. ExtractFrames.py
  3. Makefile
  4. mem.init
  5. mem_1.init
  6. synth.ys
  7. top.tcl
  8. top.xdc