Sign in
foss-fpga-tools
/
prjxray
/
6867429cc3a4ce422b06ceda100b868a0a7f8b23
/
.
/
minitests
/
litex
/
uart_ddr
/
arty
/
src.yosys
tree: ddacd9cdeb1ddc5eeaae4e2e7a31b393ba1e8fb2
mem.init
⇨
../generated/mem.init
mem_1.init
⇨
../generated/mem_1.init
Makefile
synth.ys
top.tcl