# Loosely based on
# segprint -zd test_data/clb_lut/design.bits

# LUT
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[00] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[08] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[10] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[11] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[13] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[14] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[15] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[41] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[43] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[44] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[46] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[47] 1
CLBLM_L_X10Y102.SLICE_X12Y102.ALUT.INIT[63] 1

# din bus
# din[0]
INT_L_X10Y102.CENTER_INTER_L.IMUX_L1 EE2END0
# din[1]
INT_L_X10Y102.CENTER_INTER_L.IMUX_L2 EE2END1
# din[2]
INT_L_X10Y102.CENTER_INTER_L.IMUX_L4 EE2END2
# din[3]
INT_L_X10Y102.CENTER_INTER_L.IMUX_L7 EE2END3
# din[4]
INT_L_X10Y102.CENTER_INTER_L.IMUX_L8 EL1END0
# din[5]
INT_L_X10Y102.CENTER_INTER_L.IMUX_L11 EL1END1

# dout[0]
INT_L_X10Y102.CENTER_INTER_L.WW2BEG0 LOGIC_OUTS_L12