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foss-fpga-tools/prjxray/95eb4f812b2f29ce74885abf8ecc69c72517d62f/./minitests/litex/min/arty/src.yosys
tree: db3a072a5b206ca0966d38885a6603a11d4b2aa8
  1. mem.init ⇨ ../verilog/mem.init
  2. mem_1.init ⇨ ../verilog/mem_1.init
  3. mem_2.init ⇨ ../verilog/mem_2.init
  4. Makefile
  5. synth.ys
  6. top.tcl
  7. top.xdc