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foss-fpga-tools / prjxray / 9e486828a7f776e1fe396a72e3964b5b58189eaa / . / minitests / srl
tree: 53f75e471567a6d10d8dff196ffd0ef40b1cd6db [path history] [tgz]
  1. Makefile
  2. par.tcl
  3. README.md
  4. srl32_init.v
  5. srl32_x1.v
  6. srl32_x1_and_lut6_x3.v
  7. srl32_x2.v
  8. srl32_x2_and_lut6_x2.v
  9. srl32_x2_chain.v
  10. srl32_x3.v
  11. srl32_x3_and_lut6_x1.v
  12. srl32_x3_chain.v
  13. srl32_x4.v
  14. srl32_x4_chain.v
  15. syn.tcl
minitests/srl/README.md

Minitests for SRLs

This is a minitest for various SRL configurations.

Uses Yosys to generate EDIF which is then P&R'd by Vivado. The makefile also invokes bit2fasm and segprint