)]}'
{
  "id": "7ad03d3510a006efdbe9a5f6ab3b0b899fde85aa",
  "repo": "prjxray",
  "revision": "a0dbca4da800d4748dcd3833dbd34b467d866b90",
  "path": "minitests/litex/min/arty/verilog/mem_2.init"
}