)]}'
{
  "id": "e69de29bb2d1d6434b8b29ae775ad8c2e48c5391",
  "repo": "prjxray",
  "revision": "a9dfd0b229a795bc7e4ab5b8405f9b1bb3525120",
  "path": "minitests/litex/min_ddr/arty/verilog/mem_1.init"
}