)]}'
{
  "id": "d5e10db0b60bf3b1d8f585abc697f0feac3dacf0",
  "repo": "prjxray",
  "revision": "ac25035fd4ecbc2f2401868a33e9dd3c8f156b41",
  "path": "minitests/litex/min_ddr/arty/verilog/mem.init"
}