diff --git a/.github/workflows/Pipeline.yml b/.github/workflows/Pipeline.yml
index 3653ed9..0c3410d 100644
--- a/.github/workflows/Pipeline.yml
+++ b/.github/workflows/Pipeline.yml
@@ -79,7 +79,7 @@
         env:
           XRAY_SETTINGS: ${{ matrix.family }}
 
-      - uses: actions/upload-artifact@v3
+      - uses: actions/upload-artifact@v4
         if: ${{ always() }}
         with:
           name: ${{ matrix.family }}
@@ -124,7 +124,7 @@
       - name: Run Test
         run: make test --output-sync=target --warn-undefined-variables
 
-      - uses: actions/upload-artifact@v3
+      - uses: actions/upload-artifact@v4
         if: ${{ always() }}
         with:
           path: |
diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile
index 5771695..ff87002 100644
--- a/fuzzers/005-tilegrid/Makefile
+++ b/fuzzers/005-tilegrid/Makefile
@@ -54,6 +54,9 @@
 TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += gtx_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += gtx_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb
+TILEGRID_TDB_DEPENDENCIES += gtx_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb
 endif
 
 # These kintex parts give an empty design
@@ -173,6 +176,15 @@
 gtp_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
 	cd gtp_int_interface && $(MAKE)
 
+gtx_common/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+	cd gtx_common && $(MAKE)
+
+gtx_channel/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+	cd gtx_channel && $(MAKE)
+
+gtx_int_interface/$(BUILD_FOLDER)/segbits_tilegrid.tdb: ${BASICDB_TILEGRID}
+	cd gtx_int_interface && $(MAKE)
+
 $(BUILD_FOLDER)/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES)
 	python3 add_tdb.py \
 		--fn-in ${BASICDB_TILEGRID} \
@@ -220,6 +232,9 @@
 	cd gtp_common && $(MAKE) clean
 	cd gtp_channel && $(MAKE) clean
 	cd gtp_int_interface && $(MAKE) clean
+	cd gtx_common && $(MAKE) clean
+	cd gtx_channel && $(MAKE) clean
+	cd gtx_int_interface && $(MAKE) clean
 
 clean_part:
 	rm -rf $(BUILD_FOLDER) run.${XRAY_PART}.ok
@@ -254,6 +269,9 @@
 	cd gtp_common && $(MAKE) clean_part
 	cd gtp_channel && $(MAKE) clean_part
 	cd gtp_int_interface && $(MAKE) clean_part
+	cd gtx_common && $(MAKE) clean_part
+	cd gtx_channel && $(MAKE) clean_part
+	cd gtx_int_interface && $(MAKE) clean_part
 
 .PHONY: database pushdb clean clean_part run
 
diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py
index e483f77..066be01 100644
--- a/fuzzers/005-tilegrid/add_tdb.py
+++ b/fuzzers/005-tilegrid/add_tdb.py
@@ -112,6 +112,8 @@
         ("pcie", 36, 101),
         ("gtp_common", 32, 101),
         ("gtp_channel", 32, 22),
+        ("gtx_common", 32, 101),
+        ("gtx_channel", 32, 22),
         ("clb_int", int_frames, int_words),
         ("iob_int", int_frames, int_words),
         ("iob18_int", int_frames, int_words),
@@ -123,6 +125,7 @@
         ("monitor_int", int_frames, int_words),
         ("orphan_int_column", int_frames, int_words),
         ("gtp_int_interface", int_frames, int_words),
+        ("gtx_int_interface", int_frames, int_words),
         ("pcie_int_interface", int_frames, int_words),
     ]
 
diff --git a/fuzzers/005-tilegrid/generate_full.py b/fuzzers/005-tilegrid/generate_full.py
index 454f648..cec07dd 100644
--- a/fuzzers/005-tilegrid/generate_full.py
+++ b/fuzzers/005-tilegrid/generate_full.py
@@ -557,6 +557,8 @@
     propagate_INT_INTERFACE_bits_in_column(
         database, tiles_by_grid, "GTP_INT_INTERFACE", tile_frames_map)
     propagate_INT_INTERFACE_bits_in_column(
+        database, tiles_by_grid, "GTX_INT_INTERFACE", tile_frames_map)
+    propagate_INT_INTERFACE_bits_in_column(
         database, tiles_by_grid, "PCIE_INT_INTERFACE", tile_frames_map)
     propagate_rebuf(database, tiles_by_grid)
     propagate_IOB_SING(database, tiles_by_grid)
diff --git a/fuzzers/005-tilegrid/gtx_channel/Makefile b/fuzzers/005-tilegrid/gtx_channel/Makefile
new file mode 100644
index 0000000..4144b95
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_channel/Makefile
@@ -0,0 +1,10 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 12
+GENERATE_ARGS?="--oneval 1 --design params.csv --dword 16 --dframe 1C"
+include ../fuzzaddr/common.mk
diff --git a/fuzzers/005-tilegrid/gtx_channel/generate.tcl b/fuzzers/005-tilegrid/gtx_channel/generate.tcl
new file mode 100644
index 0000000..1374d1f
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_channel/generate.tcl
@@ -0,0 +1,37 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    # Disable MMCM frequency etc sanity checks
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/005-tilegrid/gtx_channel/top.py b/fuzzers/005-tilegrid/gtx_channel/top.py
new file mode 100644
index 0000000..bddc0c1
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_channel/top.py
@@ -0,0 +1,61 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type in ['GTXE2_CHANNEL']:
+                yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top(input wire in, output wire out);
+    ''')
+
+    params = {}
+
+    sites = list(gen_sites())
+    for (tile_name, site_name), isone in zip(sites,
+                                             util.gen_fuzz_states(len(sites))):
+        params[tile_name] = (site_name, isone)
+
+        print(
+            '''
+    (* KEEP, DONT_TOUCH, LOC = "{}" *)
+   GTXE2_CHANNEL #(
+        .ALIGN_MCOMMA_DET("{}")
+    ) gtxe2_channel_{} ();'''.format(site_name, "TRUE" if isone else "FALSE", site_name))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()
diff --git a/fuzzers/005-tilegrid/gtx_common/Makefile b/fuzzers/005-tilegrid/gtx_common/Makefile
new file mode 100644
index 0000000..a432cbc
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_common/Makefile
@@ -0,0 +1,10 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 8
+GENERATE_ARGS?="--oneval 0 --design params.csv --dword 45 --dframe 1e"
+include ../fuzzaddr/common.mk
diff --git a/fuzzers/005-tilegrid/gtx_common/generate.tcl b/fuzzers/005-tilegrid/gtx_common/generate.tcl
new file mode 100644
index 0000000..eea37d7
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_common/generate.tcl
@@ -0,0 +1,36 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    # Disable MMCM frequency etc sanity checks
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-29}]
+    set_property IS_ENABLED 0 [get_drc_checks {PDRC-30}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-50}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-53}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-126}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/005-tilegrid/gtx_common/top.py b/fuzzers/005-tilegrid/gtx_common/top.py
new file mode 100644
index 0000000..c20ea2f
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_common/top.py
@@ -0,0 +1,62 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type in ['GTXE2_COMMON']:
+                yield tile_name, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top(input wire in, output wire out);
+    ''')
+
+    params = {}
+
+    sites = list(gen_sites())
+    for (tile_name, site_name), isone in zip(sites,
+                                             util.gen_fuzz_states(len(sites))):
+        params[tile_name] = (site_name, isone)
+
+        attr = 4 if isone else 5
+        print(
+            '''
+    (* KEEP, DONT_TOUCH, LOC="{site}" *)
+    GTXE2_COMMON #(
+        .QPLL_FBDIV({attr})
+    ) {site} ();'''.format(attr=attr, site=site_name))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()
diff --git a/fuzzers/005-tilegrid/gtx_int_interface/Makefile b/fuzzers/005-tilegrid/gtx_int_interface/Makefile
new file mode 100644
index 0000000..eb459dc
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_int_interface/Makefile
@@ -0,0 +1,17 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+N ?= 8
+GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1b --dword 0 --dbit 4"
+include ../fuzzaddr/common.mk
+SEGBITS=$(BUILD_DIR)/segbits_tilegrid.tdb
+$(SEGBITS): $(SPECIMENS_OK)
+	# multiple bits match for the changes, but all of those except the ones with addresses ending with 0x9b are known
+	# and not related to GTX_INT_INTERFACE
+	${XRAY_SEGMATCH} -c 6 -o $(BUILD_DIR)/segbits_tilegrid.tdb $$(find $(BUILD_DIR) -name "segdata_tilegrid.txt")
+	tr ' ' '\n' < $(SEGBITS) | grep -E 'GTX|9B' | paste -d " " - - > $(SEGBITS).tmp
+	mv -fv $(SEGBITS).tmp $(SEGBITS)
diff --git a/fuzzers/005-tilegrid/gtx_int_interface/generate.tcl b/fuzzers/005-tilegrid/gtx_int_interface/generate.tcl
new file mode 100644
index 0000000..798d66b
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_int_interface/generate.tcl
@@ -0,0 +1,86 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+proc parse_csv {} {
+    set fp [open "params.csv"]
+    set file_data [read $fp]
+    close $fp
+
+    set file_data [split $file_data "\n"]
+
+    set params_map [dict create]
+
+    set is_first_line true
+    foreach line $file_data {
+        if { $is_first_line } {
+            set is_first_line false
+            continue
+        }
+
+        # Skip empty lines
+        if { $line == "" } {
+            continue
+        }
+
+        set parts [split $line ","]
+
+        dict lappend params_map [lindex $parts 2] [lindex $parts 1]
+    }
+
+    return $params_map
+}
+
+
+proc route_through_delay {} {
+    set params_map [parse_csv]
+
+    dict for { key value } $params_map {
+        if { $value == 0 } {
+            continue
+        }
+
+        set net_name "QPLLLOCKEN_$key"
+        set net [get_nets $net_name]
+
+        set wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*GTX_INT_INTERFACE*" && NAME =~ "*IMUX_OUT24*"}]
+        set wire_parts [split $wire "/"]
+
+        set gtx_int_tile [lindex $wire_parts 0]
+        set node [get_nodes -of_object [get_tiles $gtx_int_tile] -filter { NAME =~ "*DELAY24" }]
+
+        route_design -unroute -nets $net
+        puts "Attempting to route net $net through $node."
+        route_via $net [list $node]
+    }
+}
+
+
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    # Disable MMCM frequency etc sanity checks
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
+
+    place_design
+    route_design
+
+    route_through_delay
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/005-tilegrid/gtx_int_interface/top.py b/fuzzers/005-tilegrid/gtx_int_interface/top.py
new file mode 100644
index 0000000..2ee27e0
--- /dev/null
+++ b/fuzzers/005-tilegrid/gtx_int_interface/top.py
@@ -0,0 +1,104 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+import os
+import re
+import random
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray.db import Database
+from prjxray.grid_types import GridLoc
+
+GTX_INT_Y_RE = re.compile("GTX_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
+
+
+def get_gtx_int_tile(clock_region, grid):
+    for tile_name in sorted(grid.tiles()):
+        if not tile_name.startswith("GTX_INT_INTERFACE"):
+            continue
+
+        loc = grid.loc_of_tilename(tile_name)
+
+        left_gridinfo = grid.gridinfo_at_loc(
+            GridLoc(loc.grid_x - 1, loc.grid_y))
+        right_gridinfo = grid.gridinfo_at_loc(
+            GridLoc(loc.grid_x + 1, loc.grid_y))
+
+        if left_gridinfo.tile_type in ["INT_L", "INT_R"]:
+            cmt = left_gridinfo.clock_region
+        elif right_gridinfo.tile_type in ["INT_L", "INT_R"]:
+            cmt = right_gridinfo.clock_region
+        else:
+            assert False
+
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        m = GTX_INT_Y_RE.match(tile_name)
+
+        assert m
+
+        int_y = int(m.group(1))
+
+        if clock_region == cmt and int_y % 50 == 26:
+            return tile_name
+
+
+def gen_sites():
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type in ['GTXE2_COMMON']:
+                gtx_int_tile = get_gtx_int_tile(gridinfo.clock_region, grid)
+
+                yield gtx_int_tile, site_name
+
+
+def write_params(params):
+    pinstr = 'tile,val,site\n'
+    for tile, (site, val) in sorted(params.items()):
+        pinstr += '%s,%s,%s\n' % (tile, val, site)
+    open('params.csv', 'w').write(pinstr)
+
+
+def run():
+    print('''
+module top();
+    ''')
+
+    params = {}
+
+    sites = list(gen_sites())
+    for gtx_int_tile, site_name in sites:
+        isone = random.randint(0, 1)
+
+        params[gtx_int_tile] = (site_name, isone)
+
+        print(
+            '''
+wire QPLLLOCKEN_{site};
+
+(* KEEP, DONT_TOUCH *)
+LUT1 lut_{site} (.O(QPLLLOCKEN_{site}));
+
+(* KEEP, DONT_TOUCH, LOC = "{site}" *)
+GTXE2_COMMON gtxe2_common_{site} (
+    .QPLLLOCKEN(QPLLLOCKEN_{site})
+);'''.format(site=site_name))
+
+    print("endmodule")
+    write_params(params)
+
+
+if __name__ == '__main__':
+    run()
diff --git a/fuzzers/005-tilegrid/pcie_int_interface/top.py b/fuzzers/005-tilegrid/pcie_int_interface/top.py
index 129ef8e..4bbb640 100644
--- a/fuzzers/005-tilegrid/pcie_int_interface/top.py
+++ b/fuzzers/005-tilegrid/pcie_int_interface/top.py
@@ -16,7 +16,7 @@
 from prjxray.db import Database
 from prjxray.grid_types import GridLoc
 
-GTP_INT_Y_RE = re.compile("PCIE_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
+PCIE_INT_Y_RE = re.compile("PCIE_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
 
 
 def get_pcie_int_tiles(grid, pcie_loc):
@@ -36,7 +36,7 @@
         if not tile_name.startswith("PCIE_INT_INTERFACE"):
             continue
 
-        m = GTP_INT_Y_RE.match(tile_name)
+        m = PCIE_INT_Y_RE.match(tile_name)
 
         assert m
 
diff --git a/fuzzers/005-tilegrid/util.py b/fuzzers/005-tilegrid/util.py
index 56e18ce..468ba62 100644
--- a/fuzzers/005-tilegrid/util.py
+++ b/fuzzers/005-tilegrid/util.py
@@ -105,7 +105,7 @@
 
     assert offset <= 100, (tile_name, offset)
     # Few rare cases at X=0 for double width tiles split in half => small negative offset
-    assert offset >= 0 or "IOB" in tile_name, (
+    assert offset >= 0 or "IOB" in tile_name or "GTX_INT_INTERFACE" in tile_name, (
         tile_name, hex(baseaddr), offset)
     assert 1 <= words <= 101, words
     assert offset + words <= 101, (
diff --git a/fuzzers/063-gtx-common-conf/Makefile b/fuzzers/063-gtx-common-conf/Makefile
new file mode 100644
index 0000000..1b1d1d8
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/Makefile
@@ -0,0 +1,67 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+SHELL = bash
+
+N ?= 20
+
+BUILD_DIR = build_${XRAY_PART}
+
+SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+FUZDIR ?= ${PWD}
+
+CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
+
+all: database
+
+# generate.sh / top_generate.sh call make, hence the command must
+# have a + before it.
+$(SPECIMENS_OK): $(SPECIMENS_DEPS)
+	mkdir -p ${BUILD_DIR}
+	bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
+
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.${XRAY_PART}.ok
+
+clean:
+	rm -rf ${BUILD_DIR} run.${XRAY_PART}.ok
+
+.PHONY: all run clean
+
+# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
+# as the index in the port bus
+SPECIAL_PINS = PLLRSVD1,PLLRSVD2,GTREFCLK0,GTREFCLK1,GTGREFCLK0,GTGREFCLK1,GTEASTREFCLK0,GTEASTREFCLK1,GTWESTREFCLK0,GTWESTREFCLK1,REFCLKOUTMONITOR0,REFCLKOUTMONITOR1
+
+$(BUILD_DIR)/gtxe2_common_ports.csv: generate_ports.tcl
+	env FILE_NAME=$(BUILD_DIR)/gtxe2_common_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
+
+$(BUILD_DIR)/gtxe2_common_ports.json: $(BUILD_DIR)/gtxe2_common_ports.csv
+	python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtxe2_common_pins.csv $(BUILD_DIR)/gtxe2_common_ports.json --special-pins $(SPECIAL_PINS)
+
+database: ${BUILD_DIR}/segbits_gtx_common.db $(BUILD_DIR)/gtxe2_common_ports.json
+
+${BUILD_DIR}/segbits_gtx_common.rdb: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o ${BUILD_DIR}/segbits_gtx_common.rdb $$(find $(SPECIMENS) -name "segdata_gtx_common*")
+
+${BUILD_DIR}/segbits_gtx_common.db: ${BUILD_DIR}/segbits_gtx_common.rdb
+	${XRAY_DBFIXUP} --db-root ${BUILD_DIR} --zero-db bits.dbf \
+		--seg-fn-in ${BUILD_DIR}/segbits_gtx_common.rdb \
+		--seg-fn-out ${BUILD_DIR}/segbits_gtx_common.db
+	${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtx_common.db $$(find $(SPECIMENS) -name "segdata_gtx_common*")
+
+pushdb:
+	mkdir -p $(CELLS_DATA_DIR)
+	cp attrs.json $(CELLS_DATA_DIR)/gtxe2_common_attrs.json
+	cp $(BUILD_DIR)/gtxe2_common_ports.json $(CELLS_DATA_DIR)/gtxe2_common_ports.json
+	BUILD_DIR=$(BUILD_DIR) source pushdb.sh
+
+.PHONY: database pushdb
diff --git a/fuzzers/063-gtx-common-conf/README.md b/fuzzers/063-gtx-common-conf/README.md
new file mode 100644
index 0000000..9dcf69a
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/README.md
@@ -0,0 +1,33 @@
+GTXE2\_COMMON Primitive Configuration fuzzer
+============================================
+
+This fuzzer is used to document the parameters corresponding to the GTXE2\_COMMON primitive.
+
+It uses pre-built JSON containing a dictionary of parameters, each one with four attributes:
+
+- Type: one of Binary, Integer, String, Boolean.
+- Values: all possible values that this parameter can assume. In case of `BIN` types, the values list contains only the maximum value reachable.
+- Digits: number of digits (or bits) required to use a parameter.
+- Encoding: This is present only for `INT` types of parameters. These reflect the actual encoding of the parameter value in the bit array.
+
+E.g.:
+
+```json
+{
+    "PLL0_REFCLK_DIV": {
+        "type": "INT",
+        "values": [1, 2],
+        "encoding": [16, 0],
+        "digits": 5
+    }
+}
+```
+
+In addition, there exist wires and PIPs that allow the connections of the `GTREFCLK` ports to clocks coming from the device fabric instead of the `IBUFDS_GTE2` primitive.
+
+In fact, if the clock comes from the device fabric, the physical `GTGREFCLK[01]` port is used instead of the `GTREFCLK[01]` one (even though the design's primitive port is always `GTREFCLK`).
+
+In the [User Guide (pg 27)](https://docs.amd.com/v/u/en-US/ug476_7Series_Transceivers), it is stated that the `GTGREFCLK[01]` port is used for "internal testing purposes".
+Using this port is highly discouraged to get the reference clock from the fabric, as the recommended way is to get the clock from an external source using the `IBUFDS_GTE2` primitive.
+
+Therefore, in addition to the parameters, `IN_USE` and `ZINV\INV` features, this fuzzer documents also the `GTREFCLK[01]_USED` and `BOTH_GTREFCLK[01]_USED` features.
diff --git a/fuzzers/063-gtx-common-conf/attrs.json b/fuzzers/063-gtx-common-conf/attrs.json
new file mode 100644
index 0000000..bcb25e6
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/attrs.json
@@ -0,0 +1,83 @@
+{
+    "QPLL_CFG": {
+        "type": "BIN",
+        "values": [134150145],
+        "digits": 27
+    },
+    "QPLL_CP": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "QPLL_CP_MONITOR_EN": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "QPLL_DMONITOR_SEL": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "QPLL_REFCLK_DIV": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20],
+        "encoding": [16, 0, 1, 2, 3, 5, 6, 7, 13, 14, 15],
+        "digits": 5
+    },
+    "QPLL_FBDIV": {
+        "type": "BIN",
+        "values": [496],
+        "digits": 10
+    },
+    "QPLL_FBDIV_MONITOR_EN": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "QPLL_FBDIV_RATIO": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "QPLL_LOCK_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "QPLL_INIT_CFG": {
+        "type": "BIN",
+        "values": [16777215],
+        "digits": 24
+    },
+    "QPLL_LPF": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "COMMON_CFG": {
+        "type": "BIN",
+        "values": [4294836225],
+        "digits": 32
+    },
+    "QPLL_CLKOUT_CFG": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "QPLL_COARSE_FREQ_OVRD": {
+        "type": "BIN",
+        "values": [63],
+        "digits": 5
+    },
+    "QPLL_COARSE_FREQ_OVRD_EN": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+   "BIAS_CFG": {
+        "type": "BIN",
+        "values": [18445618199572250625],
+        "digits": 64
+    }
+}
\ No newline at end of file
diff --git a/fuzzers/063-gtx-common-conf/bits.dbf b/fuzzers/063-gtx-common-conf/bits.dbf
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/bits.dbf
diff --git a/fuzzers/063-gtx-common-conf/generate.py b/fuzzers/063-gtx-common-conf/generate.py
new file mode 100644
index 0000000..6afcbb7
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/generate.py
@@ -0,0 +1,159 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+import json
+import os
+from enum import Enum
+
+from prjxray.segmaker import Segmaker
+#from icecream import ic
+
+INT = "INT"
+BIN = "BIN"
+
+
+def bitfilter_gtx_common_mid(frame, bit):
+    # Filter out non interesting bits.
+    word = int(bit / 32)
+
+    if word < 44 or word > 56:
+        return False
+
+    if frame not in [0, 1]:
+        return False
+
+    return True
+
+
+def bitfilter_gtx_common(frame, bit):
+    # Filter out non interesting bits.
+    word = int(bit / 32)
+
+    if word < 44 or word > 56:
+        return False
+
+    # let ENABLE_DRP come through
+    if (frame == 24 or frame or frame == 25) and bit == 1613:
+        return True
+    
+    if frame < 30 or frame > 31:
+        return False
+
+    return True
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    fuz_dir = os.getenv("FUZDIR", None)
+    assert fuz_dir
+    with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
+        attrs = json.load(attr_file)
+
+    print("Loading tags")
+    with open("params.json") as f:
+        params_dict = json.load(f)
+        tile_type = params_dict["tile_type"]
+        params_list = params_dict["params"]
+
+    sites_in_tile = dict()
+
+    for params in params_list:
+        site = params["site"]
+        tile = params["tile"]
+        
+        if "GTXE2_COMMON" not in site:
+            continue
+
+        sites_in_tile[tile] = site
+
+        in_use = params["IN_USE"]
+
+        segmk.add_site_tag(site, "IN_USE", in_use)
+
+        if in_use:
+            for param, param_info in attrs.items():
+                value = params[param]
+                param_type = param_info["type"]
+                param_digits = param_info["digits"]
+                param_values = param_info["values"]
+
+                if param_type == INT:
+                    param_encodings = param_info["encoding"]
+                    param_encoding = param_encodings[param_values.index(value)]
+                    bitstr = [
+                        int(x) for x in "{value:0{digits}b}".format(
+                            value=param_encoding, digits=param_digits)[::-1]
+                    ]
+
+                    for i in range(param_digits):
+                        segmk.add_site_tag(
+                            site, '%s[%u]' % (param, i), bitstr[i])
+                else:
+                    assert param_type == BIN
+                    bitstr = [
+                        int(x) for x in "{value:0{digits}b}".format(
+                            value=value, digits=param_digits)[::-1]
+                    ]
+
+                    for i in range(param_digits):
+                        segmk.add_site_tag(
+                            site, "%s[%u]" % (param, i), bitstr[i])
+
+            for param in ["QPLLLOCKDETCLK", "DRPCLK"]:
+                segmk.add_site_tag(site, "INV_" + param, params[param])
+
+            for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
+                          "BOTH_GTREFCLK_USED"]:
+                segmk.add_site_tag(site, param, params[param])
+
+            segmk.add_site_tag(site, "ENABLE_DRP", params["ENABLE_DRP"])
+
+    for params in params_list:
+        site = params["site"]
+
+        if "IBUFDS_GTE2" not in site:
+            continue
+
+        in_use = params["IN_USE"]
+        segmk.add_site_tag(site, "IN_USE", in_use)
+
+        if in_use:
+            tile = params["tile"]
+
+            for param in ["CLKRCV_TRST", "CLKCM_CFG"]:
+                value = params[param]
+                segmk.add_site_tag(site, param, "TRUE" in value)
+
+            bitstr = [
+                int(x) for x in "{value:0{digits}b}".format(
+                    value=params["CLKSWING_CFG"], digits=2)[::-1]
+            ]
+
+            gtx_common_site = sites_in_tile[tile]
+            for i in range(2):
+                segmk.add_site_tag(
+                    gtx_common_site, "IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i),
+                    bitstr[i])
+
+    if tile_type.startswith("GTX_COMMON_MID"):
+        bitfilter = bitfilter_gtx_common_mid
+    elif tile_type == "GTX_COMMON":
+        bitfilter = bitfilter_gtx_common
+    else:
+        assert False, tile_type
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+if __name__ == '__main__':
+    main()
diff --git a/fuzzers/063-gtx-common-conf/generate.tcl b/fuzzers/063-gtx-common-conf/generate.tcl
new file mode 100644
index 0000000..c720ac5
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/generate.tcl
@@ -0,0 +1,31 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-1619}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/063-gtx-common-conf/generate_ports.tcl b/fuzzers/063-gtx-common-conf/generate_ports.tcl
new file mode 100644
index 0000000..77d91ed
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/generate_ports.tcl
@@ -0,0 +1,15 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+create_project -force -name design -part $::env(XRAY_PART)
+set_property design_mode PinPlanning [current_fileset]
+open_io_design -name io_1
+
+dump_pins $::env(FILE_NAME) GTXE2_COMMON
diff --git a/fuzzers/063-gtx-common-conf/pushdb.sh b/fuzzers/063-gtx-common-conf/pushdb.sh
new file mode 100644
index 0000000..f772061
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/pushdb.sh
@@ -0,0 +1,22 @@
+#!/bin/bash
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+if ! test $(find ${BUILD_DIR} -name "segdata_gtx_common_mid_right.txt" | wc -c) -eq 0
+then
+    ${XRAY_MERGEDB} gtx_common_mid_right ${BUILD_DIR}/segbits_gtx_common.db
+    ${XRAY_MERGEDB} mask_gtx_common_mid_right ${BUILD_DIR}/mask_gtx_common.db
+    ${XRAY_MERGEDB} gtx_common_mid_left ${BUILD_DIR}/segbits_gtx_common.db
+    ${XRAY_MERGEDB} mask_gtx_common_mid_left ${BUILD_DIR}/mask_gtx_common.db
+fi
+
+if ! test $(find ${BUILD_DIR} -name "segdata_gtx_common.txt" | wc -c) -eq 0
+then
+    ${XRAY_MERGEDB} gtx_common ${BUILD_DIR}/segbits_gtx_common.db
+    ${XRAY_MERGEDB} mask_gtx_common ${BUILD_DIR}/mask_gtx_common.db
+fi
diff --git a/fuzzers/063-gtx-common-conf/top.py b/fuzzers/063-gtx-common-conf/top.py
new file mode 100644
index 0000000..21bd749
--- /dev/null
+++ b/fuzzers/063-gtx-common-conf/top.py
@@ -0,0 +1,258 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+import json
+import os
+import random
+from collections import namedtuple
+
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.lut_maker import LutMaker
+from prjxray.db import Database
+
+INT = "INT"
+BIN = "BIN"
+
+
+def gen_sites(tile, site, filter_cmt=None):
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        if tile not in gridinfo.tile_type:
+            continue
+        else:
+            tile_type = gridinfo.tile_type
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type != site:
+                continue
+
+            cmt = gridinfo.clock_region
+
+            if filter_cmt is not None and cmt != filter_cmt:
+                continue
+
+            yield tile_name, tile_type, site_name, cmt
+
+
+def main():
+    print(
+        '''
+module top(
+    input wire in,
+    output wire out
+);
+
+assign out = in;
+''')
+
+    luts = LutMaker()
+
+    params_dict = {"tile_type": None}
+    params_list = list()
+
+    clkswing_cfg_tiles = dict()
+    ibufds_out_wires = dict()
+    for tile_name, _, site_name, _ in gen_sites("GTX_COMMON", "IBUFDS_GTE2"):
+        # Both the IBUFDS_GTE2 in the same tile need to have
+        # the same CLKSWING_CFG parameter
+        if tile_name not in clkswing_cfg_tiles:
+            clkswing_cfg = random.randint(0, 3)
+            clkswing_cfg_tiles[tile_name] = clkswing_cfg
+        else:
+            clkswing_cfg = clkswing_cfg_tiles[tile_name]
+
+        in_use = bool(random.randint(0, 9))
+        params = {
+            "site":
+            site_name,
+            "tile":
+            tile_name,
+            "IN_USE":
+            in_use,
+            "CLKRCV_TRST":
+            verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
+            "CLKCM_CFG":
+            verilog.quote("TRUE" if random.randint(0, 1) else "FALSE"),
+            "CLKSWING_CFG":
+            clkswing_cfg,
+        }
+
+        if in_use:
+            ibufds_out_wire = "{}_O".format(site_name)
+
+            if tile_name not in ibufds_out_wires:
+                ibufds_out_wires[tile_name] = list()
+
+            ibufds_out_wires[tile_name].append(
+                (ibufds_out_wire, int(site_name[-1]) % 2))
+
+            print("wire {};".format(ibufds_out_wire))
+            print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
+            print(
+                """
+IBUFDS_GTE2 #(
+    .CLKRCV_TRST({CLKRCV_TRST}),
+    .CLKCM_CFG({CLKCM_CFG}),
+    .CLKSWING_CFG({CLKSWING_CFG})
+) {site} (
+    .O({out})
+);""".format(**params, out=ibufds_out_wire))
+
+        params_list.append(params)
+
+    DRP_PORTS = [
+        ("DRPCLK", "clk"), ("DRPEN", "in"), ("DRPWE", "in"), ("DRPRDY", "out")
+    ]
+
+    for tile_name, tile_type, site_name, cmt in gen_sites("GTX_COMMON",
+                                                          "GTXE2_COMMON"):
+
+        params_dict["tile_type"] = tile_type
+
+        params = dict()
+        params['site'] = site_name
+        params['tile'] = tile_name
+
+        verilog_attr = ""
+
+        verilog_attr = "#("
+
+        fuz_dir = os.getenv("FUZDIR", None)
+        assert fuz_dir
+        with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
+            attrs = json.load(attrs_file)
+
+        in_use = bool(random.randint(0, 9))
+        params["IN_USE"] = in_use
+
+        if in_use:
+            for param, param_info in attrs.items():
+                param_type = param_info["type"]
+                param_values = param_info["values"]
+                param_digits = param_info["digits"]
+
+                if param_type == INT:
+                    value = random.choice(param_values)
+                    value_str = value
+                else:
+                    assert param_type == BIN
+                    value = random.randint(0, param_values[0])
+                    value_str = "{digits}'b{value:0{digits}b}".format(
+                        value=value, digits=param_digits)
+
+                params[param] = value
+
+                verilog_attr += """
+            .{}({}),""".format(param, value_str)
+
+            verilog_ports = ""
+
+            for param in ["QPLLLOCKDETCLK", "DRPCLK"]:
+                is_inverted = random.randint(0, 1)
+
+                params[param] = is_inverted
+
+                verilog_attr += """
+            .IS_{}_INVERTED({}),""".format(param, is_inverted)
+                verilog_ports += """
+            .{}({}),""".format(param, luts.get_next_output_net())
+
+            verilog_attr = verilog_attr.rstrip(",")
+            verilog_attr += "\n)"
+
+            for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
+                          "BOTH_GTREFCLK_USED"]:
+                params[param] = 0
+
+            if tile_name in ibufds_out_wires:
+                gtrefclk_ports_used = 0
+
+                for wire, location in ibufds_out_wires[tile_name]:
+                    if random.random() < 0.5:
+                        continue
+
+                    verilog_ports += """
+            .GTREFCLK{}({}),""".format(location, wire)
+
+                    gtrefclk_ports_used += 1
+                    params["GTREFCLK{}_USED".format(location)] = 1
+
+                if gtrefclk_ports_used == 2:
+                    params["BOTH_GTREFCLK_USED"] = 1
+
+            enable_drp = random.randint(0, 1)
+            params["ENABLE_DRP"] = enable_drp
+
+            for _, _, channel_site_name, _ in gen_sites("GTX_CHANNEL",
+                                                        "GTXE2_CHANNEL", cmt):
+
+                if not enable_drp:
+                    break
+
+                verilog_ports_channel = ""
+                for port, direction in DRP_PORTS:
+                    if direction == "in":
+                        verilog_ports_channel += """
+    .{}({}),""".format(port, luts.get_next_output_net())
+
+                    elif direction == "clk":
+                        # DRPCLK needs to come from a clock source
+                        print(
+                            """
+wire clk_bufg_{site};
+
+(* KEEP, DONT_TOUCH *)
+BUFG bufg_{site} (.O(clk_bufg_{site}));""".format(site=channel_site_name))
+
+                        verilog_ports_channel += """
+    .{}(clk_bufg_{}),""".format(port, channel_site_name)
+
+                    elif direction == "out":
+                        verilog_ports_channel += """
+    .{}({}),""".format(port, luts.get_next_input_net())
+
+                print(
+                    """
+(* KEEP, DONT_TOUCH, LOC=\"{site}\" *)
+GTXE2_CHANNEL {site} (
+    {ports}
+);""".format(ports=verilog_ports_channel.rstrip(","), site=channel_site_name))
+
+            print(
+                """
+(* KEEP, DONT_TOUCH, LOC=\"{site}\" *)
+GTXE2_COMMON {attrs} {site} (
+    {ports}
+);""".format(
+                    attrs=verilog_attr,
+                    ports=verilog_ports.rstrip(","),
+                    site=site_name))
+
+        params_list.append(params)
+
+    for l in luts.create_wires_and_luts():
+        print(l)
+
+    print("endmodule")
+
+    params_dict["params"] = params_list
+    with open('params.json', 'w') as f:
+        json.dump(params_dict, f, indent=2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/fuzzers/064-gtx-channel-conf/Makefile b/fuzzers/064-gtx-channel-conf/Makefile
new file mode 100644
index 0000000..52301f2
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/Makefile
@@ -0,0 +1,66 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+SHELL = bash
+
+N ?= 40
+
+BUILD_DIR = build_${XRAY_PART}
+
+SPECIMENS := $(addprefix ${BUILD_DIR}/specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+FUZDIR ?= ${PWD}
+
+CELLS_DATA_DIR = ${XRAY_FAMILY_DIR}/cells_data
+
+all: database
+
+$(SPECIMENS_OK): $(SPECIMENS_DEPS)
+	mkdir -p ${BUILD_DIR}
+	bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@)
+
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.${XRAY_PART}.ok
+
+clean:
+	rm -rf ${BUILD_DIR} run.${XRAY_PART}.ok
+
+.PHONY: all run clean
+
+# These are pins that are hard to parse as a regexp given that the port name ends with a number, which is misinterpreted
+# as the index in the port bus
+SPECIAL_PINS = CLKRSVD0,CLKRSVD1,GTREFCLK0,GTREFCLK1,GTNORTHREFCLK0,GTNORTHREFCLK1,GTSOUTHREFCLK0,GTSOUTHREFCLK1,RXUSRCLK,RXUSRCLK2,TXUSRCLK,TXUSRCLK2,RXOSINTID0,PMARSVDIN0,PMARSVDIN1,PMARSVDIN2,PMARSVDIN3,PMARSVDIN4,PMARSVDOUT0,PMARSVDOUT1
+
+$(BUILD_DIR)/gtxe2_channel_ports.csv:
+	env FILE_NAME=$(BUILD_DIR)/gtxe2_channel_pins.csv ${XRAY_VIVADO} -mode batch -source generate_ports.tcl
+
+$(BUILD_DIR)/gtxe2_channel_ports.json: $(BUILD_DIR)/gtxe2_channel_ports.csv
+	python3 ${XRAY_UTILS_DIR}/make_ports.py $(BUILD_DIR)/gtxe2_channel_pins.csv $(BUILD_DIR)/gtxe2_channel_ports.json --special-pins $(SPECIAL_PINS)
+
+database: ${BUILD_DIR}/segbits_gtx_channelx.db $(BUILD_DIR)/gtxe2_channel_ports.json
+
+${BUILD_DIR}/segbits_gtx_channelx.rdb: $(SPECIMENS_OK)
+	find ${BUILD_DIR} -name segdata_gtx_channel_\*.txt | xargs sed -i -e 's/CHANNEL_[0-3]/CHANNEL/g'
+	${XRAY_SEGMATCH} -c 10 -o ${BUILD_DIR}/segbits_gtx_channelx.rdb $$(find $(SPECIMENS) -name "segdata_gtx_channel_[0123]*")
+
+${BUILD_DIR}/segbits_gtx_channelx.db: ${BUILD_DIR}/segbits_gtx_channelx.rdb
+	${XRAY_DBFIXUP} --db-root ${BUILD_DIR} --zero-db bits.dbf \
+		--seg-fn-in ${BUILD_DIR}/segbits_gtx_channelx.rdb \
+		--seg-fn-out ${BUILD_DIR}/segbits_gtx_channelx.db
+	${XRAY_MASKMERGE} ${BUILD_DIR}/mask_gtx_channelx.db $$(find $(SPECIMENS) -name "segdata_gtx_channel_[0123]*")
+
+pushdb:
+	mkdir -p $(CELLS_DATA_DIR)
+	cp attrs.json $(CELLS_DATA_DIR)/gtxe2_channel_attrs.json
+	cp $(BUILD_DIR)/gtxe2_channel_ports.json $(CELLS_DATA_DIR)/gtxe2_channel_ports.json
+	BUILD_DIR=$(BUILD_DIR) source pushdb.sh
+
+.PHONY: database pushdb
diff --git a/fuzzers/064-gtx-channel-conf/attrs.json b/fuzzers/064-gtx-channel-conf/attrs.json
new file mode 100644
index 0000000..7d5952c
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/attrs.json
@@ -0,0 +1,1000 @@
+{
+    "UCODEER_CLR": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RXBUFRESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RXCDRPHRESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RXCDRFREQRESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RXDFELPMRESET_TIME": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RXPMARESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RXPCSRESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RXISCANRESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "TXPCSRESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "TXPMARESET_TIME": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RX_XCLK_SEL": {
+        "type": "STR",
+        "values": ["RXREC", "RXUSR"],
+        "digits": 1
+    },
+    "CPLL_INIT_CFG": {
+        "type": "BIN",
+        "values": [16777215],
+        "digits": 24
+    },
+    "CPLL_CFG": {
+        "type": "BIN",
+        "values": [16777215],
+        "digits": 24
+    },
+    "SATA_CPLL_CFG": {
+        "type": "STR",
+        "values": ["VCO_3000MHZ", "VCO_1500MHZ", "VCO_750MHZ"],
+        "digits": 2
+    },
+    "CPLL_REFCLK_DIV": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20],
+        "encoding": [16, 0, 1, 2, 3, 5, 6, 7, 13, 14, 15],
+        "digits": 5
+    },
+    "CPLL_FBDIV_45": {
+        "type": "INT",
+        "values": [4, 5],
+        "encoding": [0, 1],
+        "digits": 1
+    },
+    "CPLL_FBDIV": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 20],
+        "encoding": [16, 0, 1, 2, 3, 5, 6, 7, 13, 14, 15],
+        "digits": 5
+    },
+    "CPLL_LOCK_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "RX_DATA_WIDTH": {
+        "type": "INT",
+        "values": [16, 20, 32, 40, 64, 80],
+        "encoding": [2, 3, 4, 5, 6, 7],
+        "digits": 3
+    },
+    "RX_INT_DATAWIDTH": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RX_CLK25_DIV": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31],
+        "digits": 5
+    },
+    "RX_CM_SEL": {
+        "type": "BIN",
+        "values": [3],
+        "digits": 2
+    },
+    "RXPRBS_ERR_LOOPBACK": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "SATA_BURST_SEQ_LEN": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "OUTREFCLK_SEL_INV": {
+        "type": "BIN",
+        "values": [3],
+        "digits": 2
+    },
+    "SATA_BURST_VAL": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "RXOOB_CFG": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "SAS_MIN_COM": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "SATA_MIN_BURST": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61],
+        "digits": 6
+    },
+    "SATA_EIDLE_VAL": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "SATA_MIN_WAKE": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "SATA_MIN_INIT": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "SAS_MAX_COM": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 71, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 71, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127],
+        "digits": 7
+    },
+    "SATA_MAX_BURST": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "SATA_MAX_WAKE": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "SATA_MAX_INIT": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "TRANS_TIME_RATE": {
+        "type": "BIN",
+        "values": [255],
+        "digits": 8
+    },
+    "TX_PREDRIVER_MODE": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "TX_LOOPBACK_DRIVE_HIZ": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "TX_DRIVE_MODE": {
+        "type": "STR",
+        "values": ["DIRECT", "PIPE", "PIPEGEN3"],
+        "digits": 5
+    },
+    "PD_TRANS_TIME_TO_P2": {
+        "type": "BIN",
+        "values": [255],
+        "digits": 8
+    },
+    "PD_TRANS_TIME_NONE_P2": {
+        "type": "BIN",
+        "values": [255],
+        "digits": 8
+    },
+    "PD_TRANS_TIME_FROM_P2": {
+        "type": "BIN",
+        "values": [4095],
+        "digits": 12
+    },
+    "PCS_PCIE_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "TXBUF_RESET_ON_RATE_CHANGE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "TXBUF_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "TXGEARBOX_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "GEARBOX_MODE": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "RX_DFE_GAIN_CFG": {
+        "type": "BIN",
+        "values": [8388607],
+        "digits": 23
+    },
+    "RX_DFE_LPM_HOLD_DURING_EIDLE": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RX_DFE_H2_CFG": {
+        "type": "BIN",
+        "values": [4095],
+        "digits": 12
+    },
+    "RX_DFE_H3_CFG": {
+        "type": "BIN",
+        "values": [4095],
+        "digits": 12
+    },
+    "RX_DFE_H4_CFG": {
+        "type": "BIN",
+        "values": [2047],
+        "digits": 11
+    },
+    "RX_DFE_H5_CFG": {
+        "type": "BIN",
+        "values": [2047],
+        "digits": 11
+    },
+    "RX_DFE_KL_CFG": {
+        "type": "BIN",
+        "values": [8191],
+        "digits": 13
+    },
+    "RX_DFE_UT_CFG": {
+        "type": "BIN",
+        "values": [131071],
+        "digits": 17
+    },
+    "RX_OS_CFG": {
+        "type": "BIN",
+        "values": [8191],
+        "digits": 13
+    },
+    "RX_DFE_VP_CFG": {
+        "type": "BIN",
+        "values": [131071],
+        "digits": 17
+    },
+    "RX_DFE_XYD_CFG": {
+        "type": "BIN",
+        "values": [8191],
+        "digits": 13
+    },
+    "RX_DFE_LPM_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "RXLPM_LF_CFG": {
+        "type": "BIN",
+        "values": [8191],
+        "digits": 13
+    },
+    "RXLPM_HF_CFG": {
+        "type": "BIN",
+        "values": [16383],
+        "digits": 14
+    },
+    "ES_QUALIFIER": {
+        "type": "BIN",
+        "values": [1208833588708967444709375],
+        "digits": 80
+    },
+    "ES_QUAL_MASK": {
+        "type": "BIN",
+        "values": [1208833588708967444709375],
+        "digits": 80
+    },
+    "ES_SDATA_MASK": {
+        "type": "BIN",
+        "values": [1208833588708967444709375],
+        "digits": 80
+    },
+    "ES_PRESCALE": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "ES_VERT_OFFSET": {
+        "type": "BIN",
+        "values": [511],
+        "digits": 9
+    },
+    "ES_HORZ_OFFSET": {
+        "type": "BIN",
+        "values": [4095],
+        "digits": 12
+    },
+    "RX_DISPERR_SEQ_MATCH": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "DEC_PCOMMA_DETECT": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "DEC_MCOMMA_DETECT": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "DEC_VALID_COMMA_ONLY": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "ES_ERRDET_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "ES_EYE_SCAN_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "ES_CONTROL": {
+        "type": "BIN",
+        "values": [63],
+        "digits": 6
+    },
+    "ALIGN_COMMA_ENABLE": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "ALIGN_MCOMMA_VALUE": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "RXSLIDE_MODE": {
+        "type": "STR",
+        "values": ["OFF", "AUTO", "PCS", "PMA"],
+        "digits": 2
+    },
+    "ALIGN_PCOMMA_VALUE": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "ALIGN_COMMA_WORD": {
+        "type": "INT",
+        "values": [1, 2, 4],
+        "encoding": [1, 2, 4],
+        "digits": 3
+    },
+    "RX_SIG_VALID_DLY": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31],
+        "digits": 5
+    },
+    "ALIGN_PCOMMA_DET": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "ALIGN_MCOMMA_DET": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "SHOW_REALIGN_COMMA": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "ALIGN_COMMA_DOUBLE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "RXSLIDE_AUTO_WAIT": {
+        "type": "INT",
+        "values": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+        "digits": 4
+    },
+    "CLK_CORRECT_USE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CLK_COR_SEQ_1_ENABLE": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "CLK_COR_SEQ_1_1": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CLK_COR_MAX_LAT": {
+        "type": "INT",
+        "values": [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60],
+        "encoding": [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60],
+        "digits": 6
+    },
+    "CLK_COR_SEQ_1_2": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CLK_COR_MIN_LAT": {
+        "type": "INT",
+        "values": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60],
+        "encoding": [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60],
+        "digits": 6
+    },
+    "CLK_COR_SEQ_1_3": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CLK_COR_REPEAT_WAIT": {
+        "type": "INT",
+        "values": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31],
+        "digits": 5
+    },
+    "CLK_COR_SEQ_1_4": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CLK_COR_SEQ_2_USE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CLK_COR_SEQ_2_ENABLE": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "CLK_COR_SEQ_2_1": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CLK_COR_KEEP_IDLE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CLK_COR_PRECEDENCE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CLK_COR_SEQ_LEN": {
+        "type": "INT",
+        "values": [1, 2, 3, 4],
+        "encoding": [0, 1, 2, 3],
+        "digits": 2
+    },
+    "CLK_COR_SEQ_2_2": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CLK_COR_SEQ_2_3": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "RXGEARBOX_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CLK_COR_SEQ_2_4": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CHAN_BOND_SEQ_1_ENABLE": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "CHAN_BOND_SEQ_1_1": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CHAN_BOND_SEQ_LEN": {
+        "type": "INT",
+        "values": [1, 2, 3, 4],
+        "encoding": [0, 1, 2, 3],
+        "digits": 2
+    },
+    "CHAN_BOND_SEQ_1_2": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CHAN_BOND_KEEP_ALIGN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CHAN_BOND_SEQ_1_3": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CHAN_BOND_SEQ_1_4": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CHAN_BOND_SEQ_2_ENABLE": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "CHAN_BOND_SEQ_2_USE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CHAN_BOND_SEQ_2_1": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "FTS_LANE_DESKEW_CFG": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "FTS_LANE_DESKEW_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "CHAN_BOND_SEQ_2_2": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "FTS_DESKEW_SEQ_ENABLE": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "CBCC_DATA_SOURCE_SEL": {
+        "type": "STR",
+        "values": ["ENCODED", "DECODED"],
+        "digits": 1
+    },
+    "CHAN_BOND_SEQ_2_3": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "CHAN_BOND_MAX_SKEW": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14],
+        "encoding": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14],
+        "digits": 4
+    },
+    "CHAN_BOND_SEQ_2_4": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "RXDLY_TAP_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "RXDLY_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "RXPH_MONITOR_SEL": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RX_DDI_SEL": {
+        "type": "BIN",
+        "values": [63],
+        "digits": 6
+    },
+    "TX_XCLK_SEL": {
+        "type": "STR",
+        "values": ["TXOUT", "TXUSR"],
+        "digits": 1
+    },
+    "RXBUF_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "TXPHDLY_CFG": {
+        "type": "BIN",
+        "values": [16711425],
+        "digits": 24
+    },
+    "TXDLY_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "TXDLY_TAP_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "TXPH_CFG": {
+        "type": "BIN",
+        "values": [65535],
+        "digits": 16
+    },
+    "TXPH_MONITOR_SEL": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "RX_BIAS_CFG": {
+        "type": "BIN",
+        "values": [4095],
+        "digits": 12
+    },
+    "TX_CLKMUX_PD": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RX_CLKMUX_PD": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "TERM_RCAL_CFG": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "TERM_RCAL_OVRD": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "TX_CLK25_DIV": {
+        "type": "INT",
+        "values": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31],
+        "digits": 5
+    },
+    "TX_QPI_STATUS_EN": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "TX_INT_DATAWIDTH": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "PMA_RSV4": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "TX_DATA_WIDTH": {
+        "type": "INT",
+        "values": [16, 20, 32, 40, 64, 80],
+        "encoding": [2, 3, 4, 5, 6, 7],
+        "digits": 3
+    },
+    "TX_EIDLE_ASSERT_DELAY": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "TX_EIDLE_DEASSERT_DELAY": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "PCS_RSVD_ATTR": {
+        "type": "BIN",
+        "values": [281462092005375],
+        "digits": 48
+    },
+    "RX_DFE_KL_CFG2": {
+        "type": "BIN",
+        "values": [511],
+        "digits": 9
+    },
+    "TX_MARGIN_FULL_1": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_FULL_0": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_FULL_3": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_FULL_2": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_LOW_0": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_FULL_4": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_LOW_2": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_LOW_1": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_LOW_4": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_MARGIN_LOW_3": {
+        "type": "BIN",
+        "values": [127],
+        "digits": 7
+    },
+    "TX_DEEMPH1": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "TX_DEEMPH0": {
+        "type": "BIN",
+        "values": [31],
+        "digits": 5
+    },
+    "TX_RXDETECT_REF": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "TX_MAINCURSOR_SEL": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "PMA_RSV3": {
+        "type": "BIN",
+        "values": [3],
+        "digits": 2
+    },
+    "TX_RXDETECT_CFG": {
+        "type": "BIN",
+        "values": [16383],
+        "digits": 14
+    },
+    "RX_CM_TRIM": {
+        "type": "BIN",
+        "values": [7],
+        "digits": 3
+    },
+    "PMA_RSV2": {
+        "type": "BIN",
+        "values": [32767],
+        "digits": 15
+    },
+    "DMONITOR_CFG": {
+        "type": "BIN",
+        "values": [16711425],
+        "digits": 24
+    },
+    "TXOUT_DIV": {
+        "type": "INT",
+        "values": [1, 2, 4, 8, 16],
+        "encoding": [0, 1, 2, 3, 4],
+        "digits": 2
+    },
+    "RXOUT_DIV": {
+        "type": "INT",
+        "values": [1, 2, 4, 8, 16],
+        "encoding": [0, 1, 2, 3, 4],
+        "digits": 2
+    },
+    "TST_RSV": {
+        "type": "BIN",
+        "values": [4294836225],
+        "digits": 32
+    },
+    "PMA_RSV": {
+        "type": "BIN",
+        "values": [4294836225],
+        "digits": 32
+    },
+    "RX_BUFFER_CFG": {
+        "type": "BIN",
+        "values": [63],
+        "digits": 6
+    },
+    "RXBUF_THRESH_OVRD": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "RXBUF_RESET_ON_EIDLE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "RXBUF_RESET_ON_CB_CHANGE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "RXBUF_RESET_ON_RATE_CHANGE": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "RXBUF_RESET_ON_COMMAALIGN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "RXBUF_THRESH_UNDFLW": {
+        "type": "INT",
+        "values": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "RXBUF_EIDLE_HI_CNT": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "RXBUF_EIDLE_LO_CNT": {
+        "type": "BIN",
+        "values": [15],
+        "digits": 4
+    },
+    "RXBUF_ADDR_MODE": {
+        "type": "STR",
+        "values": ["FULL", "FAST"],
+        "digits": 1
+    },
+    "RXBUF_THRESH_OVFLW": {
+        "type": "INT",
+        "values": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "encoding": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63],
+        "digits": 6
+    },
+    "RX_DEFER_RESET_BUF_EN": {
+        "type": "BOOL",
+        "values": ["FALSE", "TRUE"],
+        "digits": 1
+    },
+    "TXDLY_LCFG": {
+        "type": "BIN",
+        "values": [511],
+        "digits": 9
+    },
+    "RXDLY_LCFG": {
+        "type": "BIN",
+        "values": [511],
+        "digits": 9
+    },
+    "RXPH_CFG": {
+        "type": "BIN",
+        "values": [16711425],
+        "digits": 24
+    },
+    "RXPHDLY_CFG": {
+        "type": "BIN",
+        "values": [16711425],
+        "digits": 24
+    },
+    "RX_DEBUG_CFG": {
+        "type": "BIN",
+        "values": [2047],
+        "digits": 11
+    },
+    "ES_PMA_CFG": {
+        "type": "BIN",
+        "values": [1023],
+        "digits": 10
+    },
+    "RXCDR_PH_RESET_ON_EIDLE": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RXCDR_FR_RESET_ON_EIDLE": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RXCDR_HOLD_DURING_EIDLE": {
+        "type": "BIN",
+        "values": [1],
+        "digits": 1
+    },
+    "RXCDR_LOCK_CFG": {
+        "type": "BIN",
+        "values": [63],
+        "digits": 6
+    },
+    "RXCDR_CFG": {
+        "type": "BIN",
+        "values": [2361183241434822606847],
+        "digits": 71
+    }
+}
diff --git a/fuzzers/064-gtx-channel-conf/bits.dbf b/fuzzers/064-gtx-channel-conf/bits.dbf
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/bits.dbf
diff --git a/fuzzers/064-gtx-channel-conf/generate.py b/fuzzers/064-gtx-channel-conf/generate.py
new file mode 100644
index 0000000..9199023
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/generate.py
@@ -0,0 +1,147 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+import json
+import os
+from enum import Enum
+
+from prjxray.segmaker import Segmaker, add_site_group_zero
+
+INT = "INT"
+BIN = "BIN"
+BOOL = "BOOL"
+STR = "STR"
+
+
+def bitfilter_gtx_channel_x(frame, bit):
+    # Filter out interconnect bits.
+    if frame not in [28, 29, 30, 31]:
+       return False
+
+    return True
+
+
+def bitfilter_gtx_channel_x_mid(frame, bit):
+    # Filter out interconnect bits.
+    if frame not in [0, 1, 2, 3]:
+        return False
+
+    return True
+
+
+def main():
+    segmk = Segmaker("design.bits")
+
+    fuz_dir = os.getenv("FUZDIR", None)
+    assert fuz_dir
+    with open(os.path.join(fuz_dir, "attrs.json"), "r") as attr_file:
+        attrs = json.load(attr_file)
+
+    print("Loading tags")
+    with open("params.json") as f:
+        primitives_list = json.load(f)
+
+    for primitive in primitives_list:
+        tile_type = primitive["tile_type"]
+        params_list = primitive["params"]
+
+        for params in params_list:
+            site = params["site"]
+
+            if "GTXE2_CHANNEL" not in site:
+                continue
+
+            in_use = params["IN_USE"]
+
+            segmk.add_site_tag(site, "IN_USE", in_use)
+
+            if in_use:
+                for param, param_info in attrs.items():
+                    value = params[param]
+                    param_type = param_info["type"]
+                    param_digits = param_info["digits"]
+                    param_values = param_info["values"]
+
+                    if param_type == INT:
+                        param_encodings = param_info["encoding"]
+                        param_encoding = param_encodings[param_values.index(
+                            value)]
+                        bitstr = [
+                            int(x) for x in "{value:0{digits}b}".format(
+                                value=param_encoding, digits=param_digits)
+                            [::-1]
+                        ]
+
+                        for i in range(param_digits):
+                            segmk.add_site_tag(
+                                site, '%s[%u]' % (param, i), bitstr[i])
+                    elif param_type == BIN:
+                        bitstr = [
+                            int(x) for x in "{value:0{digits}b}".format(
+                                value=value, digits=param_digits)[::-1]
+                        ]
+
+                        for i in range(param_digits):
+                            segmk.add_site_tag(
+                                site, "%s[%u]" % (param, i), bitstr[i])
+                    elif param_type == BOOL:
+                        segmk.add_site_tag(site, param, value == "TRUE")
+                    else:
+                        assert param_type == STR
+
+                        # The RXSLIDE_MODE parameter has overlapping bits
+                        # for its possible values. We need to treat it
+                        # differently
+                        if param == "RXSLIDE_MODE":
+                            add_site_group_zero(
+                                segmk, site, "{}.".format(param), param_values,
+                                "OFF", value)
+                        else:
+                            for param_value in param_values:
+                                segmk.add_site_tag(
+                                    site, "{}.{}".format(param, param_value),
+                                    value == param_value)
+
+                for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
+                              "RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
+                    segmk.add_site_tag(site, "INV_" + param, params[param])
+
+    gtx_channel_x = [
+        "GTX_CHANNEL_0",
+        "GTX_CHANNEL_1",
+        "GTX_CHANNEL_2",
+        "GTX_CHANNEL_3",
+    ]
+
+    gtx_channel_x_mid = [
+        "GTX_CHANNEL_0_MID_LEFT",
+        "GTX_CHANNEL_1_MID_LEFT",
+        "GTX_CHANNEL_2_MID_LEFT",
+        "GTX_CHANNEL_3_MID_LEFT",
+        "GTX_CHANNEL_0_MID_RIGHT",
+        "GTX_CHANNEL_1_MID_RIGHT",
+        "GTX_CHANNEL_2_MID_RIGHT",
+        "GTX_CHANNEL_3_MID_RIGHT",
+    ]
+
+    if tile_type in gtx_channel_x:
+        bitfilter = bitfilter_gtx_channel_x
+    elif tile_type in gtx_channel_x_mid:
+        bitfilter = bitfilter_gtx_channel_x_mid
+    else:
+        assert False, tile_type
+
+    segmk.compile(bitfilter=bitfilter)
+    segmk.write()
+
+
+if __name__ == '__main__':
+    main()
diff --git a/fuzzers/064-gtx-channel-conf/generate.tcl b/fuzzers/064-gtx-channel-conf/generate.tcl
new file mode 100644
index 0000000..b050e95
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/generate.tcl
@@ -0,0 +1,43 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+proc run {} {
+    create_project -force -part $::env(XRAY_PART) design design
+    read_verilog top.v
+    synth_design -top top
+
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+    set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-48}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-47}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-1619}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-17}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-18}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-19}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-19}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-20}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-20}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-21}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-22}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
+    set_property IS_ENABLED 0 [get_drc_checks {REQP-51}]
+    set_property IS_ENABLED 0 [get_drc_checks {AVAL-23}]
+
+    place_design
+    route_design
+
+    write_checkpoint -force design.dcp
+    write_bitstream -force design.bit
+}
+
+run
diff --git a/fuzzers/064-gtx-channel-conf/generate_ports.tcl b/fuzzers/064-gtx-channel-conf/generate_ports.tcl
new file mode 100644
index 0000000..352ea6f
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/generate_ports.tcl
@@ -0,0 +1,15 @@
+# Copyright (C) 2017-2020  The Project X-Ray Authors
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+source "$::env(XRAY_DIR)/utils/utils.tcl"
+
+create_project -force -name design -part $::env(XRAY_PART)
+set_property design_mode PinPlanning [current_fileset]
+open_io_design -name io_1
+
+dump_pins $::env(FILE_NAME) GTXE2_CHANNEL
diff --git a/fuzzers/064-gtx-channel-conf/pushdb.sh b/fuzzers/064-gtx-channel-conf/pushdb.sh
new file mode 100644
index 0000000..28f271f
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/pushdb.sh
@@ -0,0 +1,40 @@
+#!/bin/bash
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+if ! test $(find ${BUILD_DIR} -name "segdata_gtx_channel_[0123]_mid_*.txt" | wc -c) -eq 0
+then
+    ${XRAY_MERGEDB} gtx_channel_0_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_1_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_2_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_3_mid_left ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_0_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_1_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_2_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_3_mid_left ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_0_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_1_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_2_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_3_mid_right ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_0_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_1_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_2_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_3_mid_right ${BUILD_DIR}/mask_gtx_channelx.db
+fi
+
+if ! test $(find ${BUILD_DIR} -name "segdata_gtx_channel_[0123].txt" | wc -c) -eq 0
+then
+    ${XRAY_MERGEDB} gtx_channel_0 ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_1 ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_2 ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} gtx_channel_3 ${BUILD_DIR}/segbits_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_0 ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_1 ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_2 ${BUILD_DIR}/mask_gtx_channelx.db
+    ${XRAY_MERGEDB} mask_gtx_channel_3 ${BUILD_DIR}/mask_gtx_channelx.db
+fi
diff --git a/fuzzers/064-gtx-channel-conf/top.py b/fuzzers/064-gtx-channel-conf/top.py
new file mode 100644
index 0000000..6a8d65c
--- /dev/null
+++ b/fuzzers/064-gtx-channel-conf/top.py
@@ -0,0 +1,167 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2017-2020  The Project X-Ray Authors.
+#
+# Use of this source code is governed by a ISC-style
+# license that can be found in the LICENSE file or at
+# https://opensource.org/licenses/ISC
+#
+# SPDX-License-Identifier: ISC
+
+import json
+import os
+import random
+from collections import namedtuple
+
+random.seed(int(os.getenv("SEED"), 16))
+from prjxray import util
+from prjxray import verilog
+from prjxray.lut_maker import LutMaker
+from prjxray.db import Database
+
+INT = "INT"
+BIN = "BIN"
+BOOL = "BOOL"
+STR = "STR"
+
+
+def gen_sites(site):
+    db = Database(util.get_db_root(), util.get_part())
+    grid = db.grid()
+    already_used = list()
+    for tile_name in sorted(grid.tiles()):
+        loc = grid.loc_of_tilename(tile_name)
+        gridinfo = grid.gridinfo_at_loc(loc)
+
+        if gridinfo.tile_type not in [
+                "GTX_CHANNEL_0",
+                "GTX_CHANNEL_1",
+                "GTX_CHANNEL_2",
+                "GTX_CHANNEL_3",
+                "GTX_CHANNEL_0_MID_LEFT",
+                "GTX_CHANNEL_1_MID_LEFT",
+                "GTX_CHANNEL_2_MID_LEFT",
+                "GTX_CHANNEL_3_MID_LEFT",
+                "GTX_CHANNEL_0_MID_RIGHT",
+                "GTX_CHANNEL_1_MID_RIGHT",
+                "GTX_CHANNEL_2_MID_RIGHT",
+                "GTX_CHANNEL_3_MID_RIGHT",
+        ] or gridinfo.tile_type in already_used:
+            continue
+        else:
+            tile_type = gridinfo.tile_type
+            already_used.append(tile_type)
+
+        for site_name, site_type in gridinfo.sites.items():
+            if site_type != site:
+                continue
+
+            if "RIGHT" in tile_type and "X0" in site_name:
+                continue
+
+            if "LEFT" in tile_type and "X1" in site_name:
+                continue
+
+            yield tile_name, tile_type, site_name, site_type
+
+
+def main():
+    print(
+        '''
+module top(
+    input wire in,
+    output wire out
+);
+
+assign out = in;
+''')
+
+    luts = LutMaker()
+
+    primitives_list = list()
+
+    for tile_name, tile_type, site_name, site_type in gen_sites(
+            "GTXE2_CHANNEL"):
+
+        params_list = list()
+        params_dict = dict()
+
+        params_dict["tile_type"] = tile_type
+        params = dict()
+        params['site'] = site_name
+
+        verilog_attr = ""
+
+        verilog_attr = "#("
+
+        fuz_dir = os.getenv("FUZDIR", None)
+        assert fuz_dir
+        with open(os.path.join(fuz_dir, "attrs.json"), "r") as attrs_file:
+            attrs = json.load(attrs_file)
+
+        in_use = bool(random.randint(0, 9))
+        params["IN_USE"] = in_use
+
+        if in_use:
+            for param, param_info in attrs.items():
+                param_type = param_info["type"]
+                param_values = param_info["values"]
+                param_digits = param_info["digits"]
+
+                if param_type == INT:
+                    value = random.choice(param_values)
+                    value_str = value
+                elif param_type == BIN:
+                    value = random.randint(0, param_values[0])
+                    value_str = "{digits}'b{value:0{digits}b}".format(
+                        value=value, digits=param_digits)
+                elif param_type in [BOOL, STR]:
+                    value = random.choice(param_values)
+                    value_str = verilog.quote(value)
+
+                params[param] = value
+
+                verilog_attr += """
+            .{}({}),""".format(param, value_str)
+
+            verilog_ports = ""
+            for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
+                          "RXUSRCLK", "RXUSRCLK2", "DRPCLK"]:
+                is_inverted = random.randint(0, 1)
+
+                params[param] = is_inverted
+
+                verilog_attr += """
+            .IS_{}_INVERTED({}),""".format(param, is_inverted)
+                verilog_ports += """
+            .{}({}),""".format(param, luts.get_next_output_net())
+
+            verilog_attr = verilog_attr.rstrip(",")
+            verilog_attr += "\n)"
+
+            print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
+            print(
+                """GTXE2_CHANNEL {attrs} {site} (
+    {ports}
+);
+            """.format(
+                    attrs=verilog_attr,
+                    site=tile_type.lower(),
+                    ports=verilog_ports.rstrip(",")))
+
+        params_list.append(params)
+        params_dict["params"] = params_list
+        primitives_list.append(params_dict)
+
+    for l in luts.create_wires_and_luts():
+        print(l)
+
+    print("endmodule")
+
+    with open('params.json', 'w') as f:
+        json.dump(primitives_list, f, indent=2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/fuzzers/Makefile b/fuzzers/Makefile
index 9874db6..d2947e8 100644
--- a/fuzzers/Makefile
+++ b/fuzzers/Makefile
@@ -191,6 +191,10 @@
 $(eval $(call fuzzer,065b-gtp-common-pips,005-tilegrid,part))
 $(eval $(call fuzzer,066-gtp-int-pips,005-tilegrid,all))
 endif
+ifeq ($(XRAY_DATABASE),kintex7)
+$(eval $(call fuzzer,063-gtx-common-conf,005-tilegrid,part))
+$(eval $(call fuzzer,064-gtx-channel-conf,005-tilegrid,part))
+endif
 endif
 endif
 $(eval $(call fuzzer,100-dsp-mskpat,005-tilegrid,all))
diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py
index 6689d6f..7bafec7 100644
--- a/prjxray/segmaker.py
+++ b/prjxray/segmaker.py
@@ -391,6 +391,12 @@
                 tile_type_norm = 'GTP_COMMON'
             if 'GTP_INT_INTERFACE' in tile_type_norm:
                 tile_type_norm = 'GTP_INT_INTERFACE'
+            if 'GTX_CHANNEL' in tile_type_norm:
+                tile_type_norm = 'GTX_CHANNEL'
+            if 'GTX_COMMON' in tile_type_norm:
+                tile_type_norm = 'GTX_COMMON'
+            if 'GTX_INT_INTERFACE' in tile_type_norm:
+                tile_type_norm = 'GTX_INT_INTERFACE'
 
             if tile_type_norm in ['LIOI', 'RIOI']:
                 tile_type_norm = 'IOI'
diff --git a/utils/mergedb.sh b/utils/mergedb.sh
index eae4c6d..2f8a345 100755
--- a/utils/mergedb.sh
+++ b/utils/mergedb.sh
@@ -235,6 +235,60 @@
 	gtp_int_interface)
 		cp "$2" "$tmp1" ;;
 
+	gtx_common)
+		cp "$2" "$tmp1" ;;
+
+	gtx_common_mid_left)
+		sed < "$2" > "$tmp1" -e 's/^GTX_COMMON\./GTX_COMMON_MID_LEFT./' ;;
+
+	gtx_common_mid_right)
+		sed < "$2" > "$tmp1" -e 's/^GTX_COMMON\./GTX_COMMON_MID_RIGHT./' ;;
+
+	gtx_channel_0)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_0./' ;;
+
+	gtx_channel_1)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_1./' ;;
+
+	gtx_channel_2)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_2./' ;;
+
+	gtx_channel_3)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_3./' ;;
+
+	gtx_channel_0_mid_left)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_0_MID_LEFT./' ;;
+
+	gtx_channel_1_mid_left)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_1_MID_LEFT./' ;;
+
+	gtx_channel_2_mid_left)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_2_MID_LEFT./' ;;
+
+	gtx_channel_3_mid_left)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_3_MID_LEFT./' ;;
+
+	gtx_channel_0_mid_right)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_0_MID_RIGHT./' ;;
+
+	gtx_channel_1_mid_right)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_1_MID_RIGHT./' ;;
+
+	gtx_channel_2_mid_right)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_2_MID_RIGHT./' ;;
+
+	gtx_channel_3_mid_right)
+		sed < "$2" > "$tmp1" -e 's/^GTX_CHANNEL\./GTX_CHANNEL_3_MID_RIGHT./' ;;
+
+	gtx_int_interface_l)
+		sed < "$2" > "$tmp1" -e 's/^GTX_INT_INTERFACE\.GTXE2_INT/GTX_INT_INTERFACE_L\.GTXE2_INT_LEFT/' ;;
+
+	gtx_int_interface_r)
+		sed < "$2" > "$tmp1" -e 's/^GTX_INT_INTERFACE\.GTXE2_INT/GTX_INT_INTERFACE_R\.GTXE2_INT_R/' ;;
+
+	gtx_int_interface)
+		cp "$2" "$tmp1" ;;
+
 	mask_*)
 		db=$XRAY_DATABASE_DIR/$XRAY_DATABASE/$1.db
 		ismask=true