commit ce09bfb56e147539bd50d61a00b73398be6a7c1c
author Hans Baier <foss@hans-baier.de> Sat Oct 19 07:27:32 2024 +0700
committer Hans Baier <foss@hans-baier.de> Thu Feb 13 17:20:08 2025 +0700
tree cb6bb2dad6eae2873a68b7d64860692edb5ad204
parent 8d7f18cd7d1fca37a3d8f35385b90bc890e4ded6

fuzzers/005-tilegrid/pcie_int_interface/top.py: fix PCIE_INT variable name

Signed-off-by: Hans Baier <foss@hans-baier.de>

fuzzers/005-tilegrid/pcie_int_interface/top.py

diff --git a/fuzzers/005-tilegrid/pcie_int_interface/top.py b/fuzzers/005-tilegrid/pcie_int_interface/top.py
index 129ef8e..4bbb640 100644
--- a/fuzzers/005-tilegrid/pcie_int_interface/top.py
+++ b/fuzzers/005-tilegrid/pcie_int_interface/top.py
@@ -16,7 +16,7 @@
 from prjxray.db import Database
 from prjxray.grid_types import GridLoc
 
-GTP_INT_Y_RE = re.compile("PCIE_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
+PCIE_INT_Y_RE = re.compile("PCIE_INT_INTERFACE.*X[0-9]+Y([0-9]+)")
 
 
 def get_pcie_int_tiles(grid, pcie_loc):
@@ -36,7 +36,7 @@
         if not tile_name.startswith("PCIE_INT_INTERFACE"):
             continue
 
-        m = GTP_INT_Y_RE.match(tile_name)
+        m = PCIE_INT_Y_RE.match(tile_name)
 
         assert m