Make n5FFMUX match Vivado GUI.

CLBLL_L.SLICEL_X0.D5FF.MUX.A -> CLBLL_L.SLICEL_X0.D5FFMUX.IN_A
CLBLL_L.SLICEL_X0.D5FF.MUX.B -> CLBLL_L.SLICEL_X0.D5FFMUX.IN_B

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>

fuzzers/012-clbn5ffmux/generate.py

diff --git a/fuzzers/012-clbn5ffmux/generate.py b/fuzzers/012-clbn5ffmux/generate.py
index 6c44af1..e2e5a7d 100644
--- a/fuzzers/012-clbn5ffmux/generate.py
+++ b/fuzzers/012-clbn5ffmux/generate.py
@@ -26,7 +26,7 @@
         # Theory: there is one bit for each mux positon
         # In each config 3 muxes are in one position, other 3 are in another
         inv = int(i == n)
-        segmk.addtag(loc, "%c5FF.MUX.A" % which, def_a ^ inv)
-        segmk.addtag(loc, "%c5FF.MUX.B" % which, 1 ^ def_a ^ inv)
+        segmk.addtag(loc, "%c5FFMUX.IN_A" % which, def_a ^ inv)
+        segmk.addtag(loc, "%c5FFMUX.IN_B" % which, 1 ^ def_a ^ inv)
 segmk.compile()
 segmk.write()

htmlgen/htmlgen.py

diff --git a/htmlgen/htmlgen.py b/htmlgen/htmlgen.py
index eb010ed..8f1641b 100755
--- a/htmlgen/htmlgen.py
+++ b/htmlgen/htmlgen.py
@@ -212,7 +212,7 @@
             print("  loading %s segbits." % segtype)
             with db_open("segbits_%s.db" % segtype) as f:
                 for line in f:
-                    if re.search(r"(\.[ABCD](FF|OUT)MUX\.)|(\.PRECYINIT\.)", line):
+                    if re.search(r"(\.[ABCD](5?FF|OUT)MUX\.)|(\.PRECYINIT\.)", line):
                         add_pip_bits(line)
                     else:
                         add_single_bit(line)