)]}'
{
  "id": "6ed8c8fcdf8d5fea80f1b8815ff80227bc1f341b",
  "repo": "prjxray",
  "revision": "d5f44b7158977234f44515f5fc2cbcecc603b5c0",
  "path": "minitests/litex/min/arty/verilog/VexRiscv_Lite.v"
}