)]}'
{
  "id": "d5e10db0b60bf3b1d8f585abc697f0feac3dacf0",
  "repo": "prjxray",
  "revision": "dc9060df224b79be32c886dd4e0ee0c19e47075b",
  "path": "minitests/litex/min_ddr/arty/verilog/mem.init"
}