)]}'
{
  "id": "6ed8c8fcdf8d5fea80f1b8815ff80227bc1f341b",
  "repo": "prjxray",
  "revision": "e565dae491bdef19ff8c3924264e56dd27b2bd77",
  "path": "minitests/litex/min/arty/verilog/VexRiscv_Lite.v"
}