Google Git
Sign in
foss-fpga-tools / prjxray / ed16a21cae5ff06c503455f663bc487c0ab94b55 / . / minitests / litex / min_ddr / arty / src.yosys
tree: 0e61baf053cc1323126a93260880f751c82328f5 [path history] [tgz]
  1. mem.init ⇨ ../verilog/mem.init
  2. mem_1.init ⇨ ../verilog/mem_1.init
  3. Makefile
  4. missing_bit_report.py
  5. synth.ys
  6. top.tcl
  7. top.xdc