)]}'
{
  "id": "edeb125a0fab91da81af802e9f83f9d736b72fd9",
  "repo": "prjxray",
  "revision": "f42e522731016ae8723365a7fe6feb72ee0fea1b",
  "path": "minitests/litex/min/arty/verilog/mem.init"
}