tree: 33d32025db79a7a704a5484e0bddf4360c6e4c38 [path history] [tgz]
  1. .gitignore
  2. Makefile
  3. README.md
  4. requirements.txt
minitests/litex/litepcie/README.md

LitePCIe minitest

This minitest is intended to provide a counter-prove on the possible remaining features to document for the Gigabit Transcievers (GTP tiles) and the PCIE_2_1 primitive.

It uses the following litex modules:

Repo URLSHA
https://github.com/enjoy-digital/litex7abfbd9
https://github.com/enjoy-digital/litedramab2423e
https://github.com/enjoy-digital/liteeth7448170
https://github.com/enjoy-digital/liteiclink0980a7c
https://github.com/enjoy-digital/litepcie1d7b584
https://github.com/enjoy-digital/litex-boards1d8f0a9
https://github.com/m-labs/migen40b1092
https://github.com/nmigen/nmigen490fca5
https://github.com/litex-hub/pythondata-cpu-vexriscv16c5dde

The final FASM file with the unknown bits can be obtained by running the following:

make all

All the pre-requisites (LiteX, RISC-V toolchain, etc.) are automatically installed/built. It is required though to have Vivado installed in the system.