Sign in
foss-fpga-tools
/
prjxray
/
60168e9b7e89956ce8a197f3cfdf6d4bc80926d3
/
.
/
minitests
/
srl
/
README.md
blob: c634fe1a33add059dbecbe81888e07dd7c30fac5 [
file
] [
view
]
# Minitests for SRLs
This
is
a minitest
for
various SRL configurations
.
Uses
Yosys
to generate EDIF which
is
then
P
&
R
'd by Vivado. The makefile also invokes bit2fasm and segprint