)]}'
{
  "commit": "080a18b7629f06eda214144125372d2255bb72de",
  "tree": "ee9195d893241dce1b4e9e86758979b2ed5fa10d",
  "parents": [
    "7cdb2b8949658eb8924c36f3bc6a04aaeb66395d"
  ],
  "author": {
    "name": "Maciej Kurc",
    "email": "mkurc@antmicro.com",
    "time": "Wed Jan 15 10:05:39 2020 +0100"
  },
  "committer": {
    "name": "Maciej Kurc",
    "email": "mkurc@antmicro.com",
    "time": "Mon Feb 03 13:42:39 2020 +0100"
  },
  "message": "Added generation of interconnect connections between input and output ports of the same cell if needed.\n\nSigned-off-by: Maciej Kurc \u003cmkurc@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "66f100eb4a3b4c841624a680e11326de9cd1d295",
      "old_mode": 33261,
      "old_path": "v2x/vlog_to_pbtype.py",
      "new_id": "81fc95096b3421bedca6ba1a17a350c47d3a1bb8",
      "new_mode": 33261,
      "new_path": "v2x/vlog_to_pbtype.py"
    }
  ]
}