90dc15a2d462a56db97ee1075824ed45306f3fe8 - python-symbiflow-v2x

commit: 90dc15a2d462a56db97ee1075824ed45306f3fe8
[log]
author: Karol Gugala <kgugala@antmicro.com>
Tue Feb 01 12:38:44 2022 +0100
committer: Karol Gugala <kgugala@antmicro.com>
Tue Feb 01 12:50:54 2022 +0100
tree: cfc29f7fb75e6cd055a946edbacc16c96eac23d6
parent: fa355737ce18bc00402ab2860863bb70bc4e644e [diff]

Relicense to Apache-2.0

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

.github/workflows/ci.yml[diff]
.readthedocs.yml[diff]
COPYING[Deleted - diff]
LICENSE[Added - diff]
MANIFEST.in[diff]
Makefile[diff]
docs/Makefile[diff]
docs/collect_examples.py[diff]
docs/conf.py[diff]
docs/environment.yml[diff]
docs/make_xml_for_docs.py[diff]
environment.yml[diff]
prepareenv.sh[diff]
setup.py[diff]
tests/carry/carry.sim.v[diff]
tests/carry/cblock/cblock.sim.v[diff]
tests/clock_mux/gmux.sim.v[diff]
tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v[diff]
tests/clocks/dff_one_clock/dff_one_clock.sim.v[diff]
tests/clocks/dff_two_clocks/dff_two_clocks.sim.v[diff]
tests/clocks/input_attr_clock/input_attr_clock.sim.v[diff]
tests/clocks/input_attr_not_clock/block.sim.v[diff]
tests/clocks/input_named_clk/input_named_clk.sim.v[diff]
tests/clocks/input_named_rdclk/input_named_rdclk.sim.v[diff]
tests/clocks/input_named_regex/block.sim.v[diff]
tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v[diff]
tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v[diff]
tests/clocks/output_attr_clock/output_attr_clock.sim.v[diff]
tests/clocks/output_named_clk/output_named_clk.sim.v[diff]
tests/clocks/output_named_rdclk/output_named_rdclk.sim.v[diff]
tests/dsp/dsp_combinational/dsp_combinational.sim.v[diff]
tests/dsp/dsp_in_registered/dsp_in_registered.sim.v[diff]
tests/dsp/dsp_inout_registered/dsp_inout_registered.sim.v[diff]
tests/dsp/dsp_inout_registered_dualclk/dsp_inout_registered_dualclk.sim.v[diff]
tests/dsp/dsp_modes/dsp_modes.sim.v[diff]
tests/dsp/dsp_out_registered/dsp_out_registered.sim.v[diff]
tests/dsp/dsp_partial_registered/dsp_partial_registered.sim.v[diff]
tests/gates/and/and.sim.v[diff]
tests/gates/nor/nor.sim.v[diff]
tests/gates/not/not.sim.v[diff]
tests/gates/xor/xor.sim.v[diff]
tests/internal_conn/child/child.sim.v[diff]
tests/internal_conn/parent.sim.v[diff]
tests/io/input/ipad.sim.v[diff]
tests/io/output/opad.sim.v[diff]
tests/logicbox/logicbox.sim.v[diff]
tests/modes/inv.sim.v[diff]
tests/modes/not/not.sim.v[diff]
tests/multiple_instance/multiple_instance.sim.v[diff]
tests/mux_class/mux_class.sim.v[diff]
tests/muxes/use_mux.sim.v[diff]
tests/net_attr/child/child.sim.v[diff]
tests/net_attr/parent.sim.v[diff]
tests/no_comb/ff.sim.v[diff]
tests/no_seq/lut_ff_macro.sim.v[diff]
tests/pack_pattern/dff/dff.sim.v[diff]
tests/pack_pattern/lut/lut4.sim.v[diff]
tests/pack_pattern/pack_pattern.sim.v[diff]
tests/simple_pll/simple_pll.sim.v[diff]
tests/test_v2x.py[diff]
tests/vtr/dff/dff.sim.v[diff]
tests/vtr/full-adder/adder.sim.v[diff]
tests/vtr/lutff-pair/dff/dff.sim.v[diff]
tests/vtr/lutff-pair/lut/lut4.sim.v[diff]
tests/vtr/lutff-pair/omux/omux.sim.v[diff]
tests/vtr/lutff-pair/pair.sim.v[diff]
v2x/__init__.py[diff]
v2x/__main__.py[diff]
v2x/lib/__init__.py[diff]
v2x/lib/argparse_extra.py[diff]
v2x/lib/asserts.py[diff]
v2x/lib/mux.py[diff]
v2x/mux_gen.py[diff]
v2x/vlog_to_model.py[diff]
v2x/vlog_to_pbtype.py[diff]
v2x/xmlinc/__init__.py[diff]
v2x/xmlinc/xmlinc.py[diff]
v2x/yosys/__init__.py[diff]
v2x/yosys/json.py[diff]
v2x/yosys/run.py[diff]
v2x/yosys/utils.py[diff]

81 files changed

tree: cfc29f7fb75e6cd055a946edbacc16c96eac23d6