<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <!-- https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths -->
  <model name="DFF">
    <input_ports>
      <port name="CLK" is_clock="1"/>
      <port name="D" clock="CLK"/>
    </input_ports>
    <output_ports>
      <port name="Q" clock="CLK"/>
    </output_ports>
  </model>
</models>