tree 14c7e206454e406e3ec1f54fad4e4fe97a160cf0
parent df565743f1c2259718a21ef494e80e1270f97bd4
parent 84f2898f71f40c45697ba4caae53443d49cdb439
author Tim Ansell <me@mith.ro> 1587397901 -0700
committer GitHub <noreply@github.com> 1587397901 -0700
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Merge pull request #58 from daniellimws/verilog-diagram-old

Pin verilog-diagram to an older version to stop build from failing