)]}'
{
  "commit": "332327fa7c3b89647ca8f2190730cd9b6fdd8183",
  "tree": "38666b3cf56015ed2978a6318ee0bce9b5b26780",
  "parents": [
    "0165230172d81a9f65b1269d63c3c6d392c9d746"
  ],
  "author": {
    "name": "Jeffrey Elms",
    "email": "elmsfu@freshred.net",
    "time": "Thu Mar 29 22:39:26 2018 -0700"
  },
  "committer": {
    "name": "Grzegorz Latosinski",
    "email": "glatosinski@antmicro.com",
    "time": "Mon Nov 25 11:40:39 2019 +0100"
  },
  "message": "Clarifying verilog range bound and convention\n\nSigned-off-by: Jeffrey Elms \u003celmsfu@freshred.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "223d3ef5ddb6557c2f7bd60e9057e5dbd272f970",
      "old_mode": 33261,
      "old_path": "v2x/mux_gen.py",
      "new_id": "905caf006558b0211125f445834f0bcd29d488a8",
      "new_mode": 33261,
      "new_path": "v2x/mux_gen.py"
    }
  ]
}