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{
  "commit": "3a1900a8a7d254f754a312137954049d23ce09e4",
  "tree": "8fc886f8ddb088f6b91fec697b8cfc32e55735f2",
  "parents": [
    "4bc9809986693f9029e3871152d186849d7ca766"
  ],
  "author": {
    "name": "Maciej Kurc",
    "email": "mkurc@antmicro.com",
    "time": "Wed Mar 04 12:16:20 2020 +0100"
  },
  "committer": {
    "name": "Maciej Kurc",
    "email": "mkurc@antmicro.com",
    "time": "Wed Mar 04 12:16:20 2020 +0100"
  },
  "message": "Fixed clock port inference to use a more elaborate regex than \"\u0027clk\u0027 in port name\". Added the possibility to force a port to be non-clock by setting the attribute CLOCK to 0.\n\nSigned-off-by: Maciej Kurc \u003cmkurc@antmicro.com\u003e\n",
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