docs/examples/vtr/primitive.rst

Primitive Block Timing Modeling Tutorial
========================================

The following shows examples taken from the
`Primitive Block Timing Modeling Tutorial <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#>`_
in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_.

.. include:: ../../../tests/vtr/dff/README.rst
.. include:: ../../../tests/vtr/full-adder/README.rst