tree: e8a8c824cd3358b44dd937f803d18665394d188b
  1. dff_comb_one_clock/
  2. dff_one_clock/
  3. dff_two_clocks/
  4. input_attr_clock/
  5. input_attr_not_clock/
  6. input_named_clk/
  7. input_named_rdclk/
  8. input_named_regex/
  9. multiple_inputs_named_clk/
  10. multiple_outputs_named_clk/
  11. output_attr_clock/
  12. output_named_clk/
  13. output_named_rdclk/
  14. README.md
tests/clocks/README.md

clocks tests

This directory contains test for the clock detection functionality for the vlog_to_model.py and vlog_to_pbtype.py tool.

Detection of clock signals

  • [ ] Signal name matches the regexp [a-z_]*clk[a-z0-9]*$
  • [ ] Manually set via the (* CLOCK *) or (* CLOCK=1 *) Verilog attribute.
  • [ ] Manually cleared via the (* CLOCK=0 *) Verilog attribute.
  • [ ] Signal drives synchronous logic (IE flipflop).
  • [ ] Detection in recursive module includes.

Detection of clock association

  • [ ] Clock comes from synchronous logic
  • [ ] Manually associated via (* ASSOC_CLOCK="<clock signal"> *) Verilog attribute.
  • [ ] Detection in recursive module includes.