Full Adder Example

An example of the classical combinational “full adder” circuit.

This is shown in Figure 41 - Full Adder of the “Combinational block” section in the Primitive Block Timing Modeling Tutorial of the Verilog to Routing documentation and reproduced below;

Fig. 41 Full Adder

Detection of combinational connections

• [ ] output has combinational connection with input

Blackbox detection

• [ ] model of the leaf pb_type is generated
• [ ] leaf pb_type XML is generated

Timings

• [ ] all the timings defined for wires with attributes should be included in pb_type XML