AND gate
========

This is an AND gate

.. symbolator:: and.sim.v

.. verilog-diagram:: and.sim.v
   :type: netlistsvg
   :module: AND

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.. no-license:: and.sim.v
   :language: verilog
   :caption: and.sim.v

The gate model generated by V2X

.. literalinclude:: and.model.xml
   :language: xml
   :caption: and.model.xml

The gate pb_type generated by V2X

.. literalinclude:: and.pb_type.xml
   :language: xml
   :caption: and.pb_type.xml