Fixed clock port inference to use a more elaborate regex than "'clk' in port name". Added the possibility to force a port to be non-clock by setting the attribute CLOCK to 0. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.
Documentation can be found at https://python-symbiflow-v2x.readthedocs.io/en/latest/