diff --git a/setup.py b/setup.py
index 8b634a5..47df2b2 100644
--- a/setup.py
+++ b/setup.py
@@ -17,9 +17,7 @@
 setuptools.setup(
     name="v2x",
     version="0.0.1",
-    entry_points={
-        "console_scripts": ["v2x=v2x.__main__:v2x"]
-    },
+    entry_points={"console_scripts": ["v2x=v2x.__main__:v2x"]},
     author="SymbiFlow Authors",
     author_email="symbiflow@lists.librecores.org",
     description="Python library for generating VPR architecture \
diff --git a/v2x/__main__.py b/v2x/__main__.py
index 7978002..8791a2f 100644
--- a/v2x/__main__.py
+++ b/v2x/__main__.py
@@ -26,18 +26,18 @@
 
     if args.mode == "pb_type":
         with open(args.outfile, "w") as fp:
-            fp.write(vlog_to_pbtype.vlog_to_pbtype(
-                args.infiles, args.outfile, args.top))
+            fp.write(
+                vlog_to_pbtype.vlog_to_pbtype(
+                    args.infiles, args.outfile, args.top))
     else:
         with open(args.outfile, "w") as fp:
-            fp.write(vlog_to_model.vlog_to_model(
-                args.infiles, args.includes, args.top, args.outfile))
+            fp.write(
+                vlog_to_model.vlog_to_model(
+                    args.infiles, args.includes, args.top, args.outfile))
 
 
 def v2x():
-    parser = argparse.ArgumentParser(
-        description="Verilog to XML"
-    )
+    parser = argparse.ArgumentParser(description="Verilog to XML")
     parser.add_argument(
         'infiles',
         metavar='input.v',
@@ -47,15 +47,13 @@
 One or more Verilog input files, that will be passed to Yosys internally.
 They should be enough to generate a flattened representation of the model,
 so that paths through the model can be determined.
-"""
-    )
+""")
     parser.add_argument(
         '--top',
         help="""\
 Top level module, will usually be automatically determined from the file name
 %.sim.v
-"""
-    )
+""")
     parser.add_argument(
         '--outfile',
         '-o',
@@ -63,15 +61,13 @@
         default="output.xml",
         help="""\
 Output filename, default 'output.xml'
-"""
-    )
+""")
     parser.add_argument(
         '--includes',
         help="""\
 Comma separate list of include directories.
 """,
-        default=""
-    )
+        default="")
     parser.add_argument(
         '--mode',
         type=str,
@@ -80,8 +76,7 @@
         help="""\
 Output file type, possible values are: pb_type and model.
 Default value is pb_type
-"""
-    )
+""")
     args = parser.parse_args()
     sys.exit(main(args))
 
diff --git a/v2x/lib/argparse_extra.py b/v2x/lib/argparse_extra.py
index 4dc1ab3..7babe4b 100644
--- a/v2x/lib/argparse_extra.py
+++ b/v2x/lib/argparse_extra.py
@@ -71,8 +71,7 @@
             default=None,
             required=False,
             help=None,
-            metavar=None
-    ):
+            metavar=None):
         self.orig_option_strings = option_strings
         new_option_strings = []
         for s in option_strings:
@@ -90,8 +89,7 @@
             choices=None,
             required=required,
             help=help,
-            metavar=metavar
-        )
+            metavar=metavar)
 
     def value(self, s):
         if not s:
@@ -113,8 +111,7 @@
 
     def __repr__(self):
         return "ActionStoreBool({}, {})".format(
-            self.orig_option_strings, self.default
-        )
+            self.orig_option_strings, self.default)
 
 
 if __name__ == "__main__":
diff --git a/v2x/lib/asserts.py b/v2x/lib/asserts.py
index b2d7b5c..1fcd4e0 100644
--- a/v2x/lib/asserts.py
+++ b/v2x/lib/asserts.py
@@ -37,8 +37,7 @@
 def assert_not_in(needle, haystack, msg=None):
     """Assert equal with better error message."""
     assert needle not in haystack, msg or __safe_error(
-        "already in", needle, haystack
-    )
+        "already in", needle, haystack)
 
 
 def assert_is(a, b):
@@ -47,8 +46,7 @@
 
 
 def assert_type(
-        obj, cls, msg="{obj} ({obj!r}) should be a {cls}, not {objcls}"
-):
+        obj, cls, msg="{obj} ({obj!r}) should be a {cls}, not {objcls}"):
     """Raise a type error if obj is not an instance of cls."""
     if not isinstance(obj, cls):
         raise TypeError(msg.format(obj=obj, objcls=type(obj), cls=cls))
@@ -65,9 +63,5 @@
     # Sanity check
     max_len = max(len(p) for p in v)
     for i, p in enumerate(v):
-        assert len(
-            p
-        ) == max_len, "Length check failed!\n \
-v[{}] has {} elements != {} ({!r})\n{!r}".format(
-            i, len(p), max_len, p, v
-        )
+        assert len(p) == max_len, "Length check failed!\n \
+v[{}] has {} elements != {} ({!r})\n{!r}".format(i, len(p), max_len, p, v)
diff --git a/v2x/lib/mux.py b/v2x/lib/mux.py
index 68b954a..596df19 100644
--- a/v2x/lib/mux.py
+++ b/v2x/lib/mux.py
@@ -63,8 +63,7 @@
             return "output wire"
         else:
             raise TypeError(
-                "Can't convert {} into verilog definition.".format(self)
-            )
+                "Can't convert {} into verilog definition.".format(self))
 
     def direction(self):
         if self in (self.INPUT, self.SELECT):
@@ -73,8 +72,7 @@
             return "output"
         else:
             raise TypeError(
-                "Can't convert {} into verilog definition.".format(self)
-            )
+                "Can't convert {} into verilog definition.".format(self))
 
     def __str__(self):
         return self.value
@@ -92,14 +90,12 @@
         if self.width == 1:
             if self.data_width is not None and self.data_width > 1:
                 return '\t%s [%d:0] %s;\n' % (
-                    self.pin_type.verilog(), self.data_width - 1, self.name
-                )
+                    self.pin_type.verilog(), self.data_width - 1, self.name)
             else:
                 return '\t%s %s;\n' % (self.pin_type.verilog(), self.name)
         else:
             return '\t%s %s %s;\n' % (
-                self.pin_type.verilog(), self.index, self.name
-            )
+                self.pin_type.verilog(), self.index, self.name)
 
 
 def pb_type_xml(mux_type, mux_name, pins, subckt=None, num_pb=1, comment=""):
@@ -131,8 +127,8 @@
     xml.etree.ElementTree
         pb_type.xml for requested mux
     """
-    assert isinstance(comment,
-                      str), "{} {}".format(type(comment), repr(comment))
+    assert isinstance(comment, str), "{} {}".format(
+        type(comment), repr(comment))
 
     if mux_type not in (MuxType.LOGIC, MuxType.ROUTING):
         assert False, "Unknown type {}".format(mux_type)
@@ -141,8 +137,7 @@
         'pb_type', {
             'name': mux_name,
             'num_pb': str(num_pb),
-        }
-    )
+        })
 
     if mux_type == MuxType.LOGIC:
         add_metadata(pb_type_xml, 'bel', 'mux')
@@ -154,8 +149,7 @@
         model.text = '.subckt {}'.format(subckt)
     else:
         assert not subckt, "Provided subckt={} for non-logic mux!".format(
-            subckt
-        )
+            subckt)
 
     if comment is not None:
         pb_type_xml.append(ET.Comment(comment))
@@ -171,8 +165,7 @@
 
         assert port.width == 1 or port.data_width == 1, (
             'Only one of width(%d) or data_width(%d) may > 1 for pin %s' %
-            (port.width, port.data_width, port.name)
-        )
+            (port.width, port.data_width, port.name))
 
         if port.width == 1 and port.data_width > 1:
             num_pins = port.data_width
@@ -244,8 +237,7 @@
 
         meta_fasm_mux = ET.SubElement(meta_root, 'meta', {'key': 'fasm_mux'})
         meta_fasm_mux.text = "\n".join(
-            [""] + ["{0} = {0}".format(i) for i in inputs] + [""]
-        )
+            [""] + ["{0} = {0}".format(i) for i in inputs] + [""])
 
     return pb_type_xml
 
diff --git a/v2x/mux_gen.py b/v2x/mux_gen.py
index 7b78d4a..eb6efb9 100755
--- a/v2x/mux_gen.py
+++ b/v2x/mux_gen.py
@@ -8,7 +8,6 @@
 # https://opensource.org/licenses/ISC
 #
 # SPDX-License-Identifier:	ISC
-
 """
 Generate MUX.
 
@@ -30,54 +29,46 @@
 parser = argparse.ArgumentParser(
     description='Generate a MUX wrapper.',
     fromfile_prefix_chars='@',
-    prefix_chars='-~'
-)
+    prefix_chars='-~')
 
 parser.add_argument(
     '--verbose',
     '--no-verbose',
     action=ActionStoreBool,
     default=os.environ.get('V', '') == '1',
-    help="Print lots of information about the generation."
-)
+    help="Print lots of information about the generation.")
 
 parser.add_argument('--width', type=int, default=8, help="Width of the MUX.")
 
 parser.add_argument(
-    '--data-width', type=int, default=1, help="data width of the MUX."
-)
+    '--data-width', type=int, default=1, help="data width of the MUX.")
 
 parser.add_argument(
     '--type',
     choices=['logic', 'routing'],
     default='logic',
-    help="Type of MUX."
-)
+    help="Type of MUX.")
 
 parser.add_argument(
     '--split-inputs',
     action=ActionStoreBool,
     default=False,
-    help="Split the inputs into separate signals"
-)
+    help="Split the inputs into separate signals")
 
 parser.add_argument(
     '--split-selects',
     action=ActionStoreBool,
     default=False,
-    help="Split the selects into separate signals"
-)
+    help="Split the selects into separate signals")
 
 parser.add_argument(
-    '--name-mux', type=str, default='MUX', help="Name of the mux."
-)
+    '--name-mux', type=str, default='MUX', help="Name of the mux.")
 
 parser.add_argument(
     '--name-input',
     type=str,
     default='I',
-    help="Name of the input values for the mux."
-)
+    help="Name of the input values for the mux.")
 
 parser.name_inputs = parser.add_argument(
     '--name-inputs',
@@ -92,15 +83,13 @@
     '--name-output',
     type=str,
     default='O',
-    help="Name of the output value for the mux."
-)
+    help="Name of the output value for the mux.")
 
 parser.add_argument(
     '--name-select',
     type=str,
     default='S',
-    help="Name of the select parameter for the mux."
-)
+    help="Name of the select parameter for the mux.")
 
 parser.name_selects = parser.add_argument(
     '--name-selects',
@@ -108,8 +97,7 @@
     default=None,
     help=  # noqa: E251
     "Comma deliminator list for the name of each select to the mux " +
-    "(implies --split-selects)."
-)
+    "(implies --split-selects).")
 
 parser.add_argument(
     '--order',
@@ -118,54 +106,48 @@
     default='iso',
     help=  # noqa: E251
     """Order of the arguments for the MUX.
-(i - Inputs, o - Output, s - Select)"""
-)
+(i - Inputs, o - Output, s - Select)""")
 
 parser.add_argument(
     '--outdir',
     default=None,
-    help="""Directory to output generated content too."""
-)
+    help="""Directory to output generated content too.""")
 
 parser.add_argument(
     '--outfilename',
     default=None,
-    help="""Filename to output generated content too."""
-)
+    help="""Filename to output generated content too.""")
 
 parser.add_argument(
-    '--comment', default=None, help="""Add some type of comment to the mux."""
-)
+    '--comment', default=None, help="""Add some type of comment to the mux.""")
 
 parser.add_argument(
-    '--num_pb', default=1, help="""Set the num_pb for the mux."""
-)
+    '--num_pb', default=1, help="""Set the num_pb for the mux.""")
 
 parser.add_argument(
-    '--subckt', default=None, help="""Override the subcircuit name."""
-)
+    '--subckt', default=None, help="""Override the subcircuit name.""")
 
 
-def mux_gen(argv=('Python function', ),
-            width=8,
-            data_width=1,
-            datatype='logic',
-            split_inputs=False,
-            split_selects=False,
-            name_mux='MUX',
-            name_input='I',
-            name_inputs=None,
-            name_output='O',
-            name_select='S',
-            name_selects=None,
-            order='iso',
-            outdir=None,
-            outfilename=None,
-            comment=None,
-            num_pb=1,
-            subckt=None,
-            verbose=False
-            ):
+def mux_gen(
+        argv=('Python function', ),
+        width=8,
+        data_width=1,
+        datatype='logic',
+        split_inputs=False,
+        split_selects=False,
+        name_mux='MUX',
+        name_input='I',
+        name_inputs=None,
+        name_output='O',
+        name_select='S',
+        name_selects=None,
+        order='iso',
+        outdir=None,
+        outfilename=None,
+        comment=None,
+        num_pb=1,
+        subckt=None,
+        verbose=False):
     def output_block(name, s):
         if verbose:
             print()
@@ -195,8 +177,7 @@
 
     if data_width > 1 and not split_inputs:
         assert False, "data_width(%d) > 1 requires using split_inputs" % (
-            data_width
-        )
+            data_width)
 
     name_input_default = 'I'
     name_inputs_default = None
@@ -209,14 +190,11 @@
         split_inputs = True
 
         names = name_inputs.split(',')
-        assert len(names) == width, "%s input names, but %s needed." % (
-            names, width
-        )
+        assert len(
+            names) == width, "%s input names, but %s needed." % (names, width)
         name_inputs = names
     elif split_inputs:
-        name_inputs = [
-            name_input + str(i) for i in range(width)
-        ]
+        name_inputs = [name_input + str(i) for i in range(width)]
         name_inputs_default = name_inputs
         assert_eq(name_inputs_default, name_inputs)
 
@@ -227,13 +205,10 @@
 
         names = name_selects.split(',')
         assert len(names) == width_bits, (
-            "%s select names, but %s needed." % (names, width_bits)
-        )
+            "%s select names, but %s needed." % (names, width_bits))
         name_selects = names
     elif split_selects:
-        name_selects = [
-            name_select + str(i) for i in range(width_bits)
-        ]
+        name_selects = [name_select + str(i) for i in range(width_bits)]
         name_selects.default = name_selects
         assert_eq(name_selects_default, name_selects)
 
@@ -266,43 +241,33 @@
             if split_inputs:
                 port_names.extend(
                     mux_lib.ModulePort(
-                        mux_lib.MuxPinType.INPUT, name_inputs[j], 1,
-                        '[%i]' % j, data_width
-                    ) for j in range(width)
-                )
+                        mux_lib.MuxPinType.INPUT, name_inputs[j], 1, '[%i]' %
+                        j, data_width) for j in range(width))
             else:
-                # verilog range bounds are inclusive and convention is [<width-1>:0]
+                # verilog range bounds are inclusive and convention is
+                # [<width-1>:0]
                 port_names.append(
                     mux_lib.ModulePort(
                         mux_lib.MuxPinType.INPUT, name_input, width,
-                        '[%i:0]' % (width - 1)
-                    )
-                )
+                        '[%i:0]' % (width - 1)))
         elif i == 's':
             if split_selects:
                 port_names.extend(
                     mux_lib.ModulePort(
-                        mux_lib.MuxPinType.SELECT, name_selects[j], 1,
-                        '[%i]' % j
-                    ) for j in range(width_bits)
-                )
+                        mux_lib.MuxPinType.SELECT, name_selects[j], 1, '[%i]' %
+                        j) for j in range(width_bits))
             else:
                 # verilog range bounds are inclusive and convention is
                 # [<width-1>:0]
                 assert name_select is not None
                 port_names.append(
                     mux_lib.ModulePort(
-                        mux_lib.MuxPinType.SELECT, name_select,
-                        width_bits, '[%i:0]' % (width_bits - 1)
-                    )
-                )
+                        mux_lib.MuxPinType.SELECT, name_select, width_bits,
+                        '[%i:0]' % (width_bits - 1)))
         elif i == 'o':
             port_names.append(
                 mux_lib.ModulePort(
-                    mux_lib.MuxPinType.OUTPUT, name_output, 1, '',
-                    data_width
-                )
-            )
+                    mux_lib.MuxPinType.OUTPUT, name_output, 1, '', data_width))
 
     # ------------------------------------------------------------------------
     # Generate the techmap Verilog module
@@ -313,8 +278,8 @@
         with open(techmap_pathname, "w") as f:
             module_args = []
             for port in port_names:
-                if (datatype == 'routing' and
-                        port.pin_type == mux_lib.MuxPinType.SELECT):
+                if (datatype == 'routing'
+                        and port.pin_type == mux_lib.MuxPinType.SELECT):
                     continue
                 module_args.append(port.name)
 
@@ -324,8 +289,7 @@
 
             f.write(
                 "module %s(%s);\n" %
-                (name_mux.upper(), ", ".join(module_args))
-            )
+                (name_mux.upper(), ", ".join(module_args)))
             f.write('\tparameter MODE = "";\n')
 
             modes = [
@@ -346,9 +310,8 @@
             f.write('\tgenerate\n')
             for i, mode in enumerate(modes):
                 f.write(
-                    '\t\t%s ( MODE == "%s" )\n' %
-                    (('if', 'else if')[i > 0], mode)
-                )
+                    '\t\t%s ( MODE == "%s" )\n' % (
+                        ('if', 'else if')[i > 0], mode))
                 f.write('\t\tbegin\n')
                 f.write('\t\t\tassign %s = %s;\n' % (outputs[0], mode))
                 f.write('\t\tend\n')
@@ -366,8 +329,8 @@
     with open(sim_pathname, "w") as f:
         module_args = []
         for port in port_names:
-            if (datatype == 'routing' and
-                    port.pin_type == mux_lib.MuxPinType.SELECT):
+            if (datatype == 'routing'
+                    and port.pin_type == mux_lib.MuxPinType.SELECT):
                 continue
             module_args.append(port.name)
 
@@ -388,8 +351,7 @@
                     width,
                     '',
                     width,
-                )
-            )
+                ))
         f.write("\n")
         f.write('(* CLASS="%s" *)\n' % mux_class)
 
@@ -411,16 +373,14 @@
 
         f.write('(* whitebox *)\n')
         f.write(
-            "module %s(%s);\n" %
-            (name_mux.upper(), ", ".join(module_args))
-        )
+            "module %s(%s);\n" % (name_mux.upper(), ", ".join(module_args)))
         previous_type = None
         for port in port_names:
             if previous_type != port.pin_type:
                 f.write("\n")
                 previous_type = port.pin_type
-            if (datatype == 'routing' and
-                    port.pin_type == mux_lib.MuxPinType.SELECT):
+            if (datatype == 'routing'
+                    and port.pin_type == mux_lib.MuxPinType.SELECT):
                 f.write('\tparameter MODE = "";\n')
             else:
                 f.write(port.getDefinition())
@@ -428,9 +388,7 @@
         f.write("\n")
         if data_width > 1:
             f.write('\tgenvar\tii;\n')
-            f.write(
-                '\tfor(ii=0; ii<%d; ii++) begin: bitmux\n' % (data_width)
-            )
+            f.write('\tfor(ii=0; ii<%d; ii++) begin: bitmux\n' % (data_width))
 
         if datatype == 'logic':
             f.write('\tMUX%s mux (\n' % width)
@@ -481,19 +439,18 @@
             f.write('\tgenerate\n')
             for i, mode in enumerate(modes):
                 f.write(
-                    '\t\t%s ( MODE == "%s" )\n' %
-                    (('if', 'else if')[i > 0], mode)
-                )
+                    '\t\t%s ( MODE == "%s" )\n' % (
+                        ('if', 'else if')[i > 0], mode))
                 f.write('\t\tbegin:SELECT_%s\n' % mode)
                 f.write('\t\t\tassign %s = %s;\n' % (outputs[0], mode))
                 f.write('\t\tend\n')
             f.write('\t\telse\n')
             f.write('\t\tbegin\n')
             f.write(
-                ('\t\t\t//$error("%s: Invalid routing value %%s ' +
-                    '(options are: %s)", MODE);\n')
-                % (name_mux, ", ".join(modes))
-            )
+                (
+                    '\t\t\t//$error("%s: Invalid routing value %%s ' +
+                    '(options are: %s)", MODE);\n') %
+                (name_mux, ", ".join(modes)))
             f.write('\t\tend\n')
             f.write('\tendgenerate\n')
 
@@ -531,14 +488,13 @@
                 ET.SubElement(
                     input_ports, 'port', {
                         'name':
-                            port.name,
+                        port.name,
                         'combinational_sink_ports':
-                            ' '.join(
-                                port.name for port in port_names if
-                                port.pin_type in (mux_lib.MuxPinType.OUTPUT, )
-                            ),
-                    }
-                )
+                        ' '.join(
+                            port.name
+                            for port in port_names
+                            if port.pin_type in (mux_lib.MuxPinType.OUTPUT, )),
+                    })
             elif port.pin_type in (mux_lib.MuxPinType.OUTPUT, ):
                 ET.SubElement(output_ports, 'port', {'name': port.name})
 
@@ -574,26 +530,27 @@
 def main(argv):
     args = parser.parse_args()
 
-    mux_gen(argv=argv,
-            width=args.width,
-            data_width=args.data_width,
-            datatype=args.type,
-            split_inputs=args.split_inputs,
-            split_selects=args.split_selects,
-            name_mux=args.name_mux,
-            name_input=args.name_input,
-            name_inputs=args.name_inputs,
-            name_output=args.name_output,
-            name_select=args.name_select,
-            name_selects=args.name_selects,
-            order=args.order,
-            outdir=args.outdir,
-            outfilename=args.outfilename,
-            comment=args.comment,
-            num_pb=args.num_pb,
-            subckt=args.subckt,
-            verbose=args.verbose,
-            )
+    mux_gen(
+        argv=argv,
+        width=args.width,
+        data_width=args.data_width,
+        datatype=args.type,
+        split_inputs=args.split_inputs,
+        split_selects=args.split_selects,
+        name_mux=args.name_mux,
+        name_input=args.name_input,
+        name_inputs=args.name_inputs,
+        name_output=args.name_output,
+        name_select=args.name_select,
+        name_selects=args.name_selects,
+        order=args.order,
+        outdir=args.outdir,
+        outfilename=args.outfilename,
+        comment=args.comment,
+        num_pb=args.num_pb,
+        subckt=args.subckt,
+        verbose=args.verbose,
+    )
 
 
 if __name__ == "__main__":
diff --git a/v2x/vlog_to_model.py b/v2x/vlog_to_model.py
index 88e99a8..98bc4ee 100755
--- a/v2x/vlog_to_model.py
+++ b/v2x/vlog_to_model.py
@@ -8,7 +8,6 @@
 # https://opensource.org/licenses/ISC
 #
 # SPDX-License-Identifier:	ISC
-
 """
 Convert a Verilog simulation model to a VPR `model.xml`
 
@@ -60,14 +59,10 @@
     -------
     is_clock_assoc: bool
     """
-    clock_assoc_signals = run.get_clock_assoc_signals(
-        infiles, module, clk
-    )
+    clock_assoc_signals = run.get_clock_assoc_signals(infiles, module, clk)
 
     if direction == "input":
-        assoc_outputs = run.get_related_output_for_input(
-            infiles, module, port
-        )
+        assoc_outputs = run.get_related_output_for_input(infiles, module, port)
         for out in assoc_outputs:
             if out in clock_assoc_signals:
                 return True
@@ -104,8 +99,9 @@
     # Check Yosys version
     pfx = run.determine_select_prefix()
     if pfx != "=":
-        print("ERROR The version of Yosys found is outdated and not supported"
-              " by V2X")
+        print(
+            "ERROR The version of Yosys found is outdated and not supported"
+            " by V2X")
         sys.exit(-1)
 
     iname = os.path.basename(infiles[0])
@@ -133,8 +129,7 @@
                 print(
                     """\
     ERROR file name not of format %.sim.v ({}), cannot detect top level.
-    Manually specify the top level module using --top"""
-                ).format(iname)
+    Manually specify the top level module using --top""").format(iname)
                 sys.exit(1)
 
     assert top is not None
@@ -143,8 +138,7 @@
         print(
             """\
     ERROR: more than one module in design, cannot detect top level.
-    Manually specify the top level module using --top"""
-        )
+    Manually specify the top level module using --top""")
         sys.exit(1)
 
     tmod = yj.top_module
@@ -173,19 +167,15 @@
             if wm:
                 model_path = "{}/{}.model.xml".format(
                     module_path,
-                    wm.group(1).lower()
-                )
+                    wm.group(1).lower())
             else:
                 assert False, "included Verilog file name {} does \
-                        not follow pattern %%.sim.v".format(
-                    module_basename
-                )
+                        not follow pattern %%.sim.v".format(module_basename)
             xmlinc.include_xml(
                 parent=models_xml,
                 href=model_path,
                 outfile=outfile,
-                xptr="xpointer(models/child::node())"
-            )
+                xptr="xpointer(models/child::node())")
     else:
         # Is a leaf model
         topname = tmod.attr("MODEL_NAME", top)
@@ -231,8 +221,7 @@
                 else:
                     clks = list()
                     for clk in clocks:
-                        if is_clock_assoc(
-                           infiles, top, clk, name, iodir):
+                        if is_clock_assoc(infiles, top, clk, name, iodir):
 
                             clks.append(clk)
                         if clks and int(port_attrs.get("NO_SEQ", 0)) == 0:
@@ -250,7 +239,7 @@
                                   in VPR models"
 
     if len(models_xml) == 0:
-        models_xml.insert(0,
-                          ET.Comment("this file is intentionally left blank"))
+        models_xml.insert(
+            0, ET.Comment("this file is intentionally left blank"))
 
     return ET.tostring(models_xml, pretty_print=True).decode('utf-8')
diff --git a/v2x/vlog_to_pbtype.py b/v2x/vlog_to_pbtype.py
index 94be02b..99bdb26 100755
--- a/v2x/vlog_to_pbtype.py
+++ b/v2x/vlog_to_pbtype.py
@@ -8,7 +8,6 @@
 # https://opensource.org/licenses/ISC
 #
 # SPDX-License-Identifier:	ISC
-
 """\
 Convert a Verilog simulation model to a VPR `pb_type.xml`
 
@@ -99,8 +98,8 @@
     normalized_name = pb_name.replace('.', '_')
     if index is not None:
         normalized_name = normalized_name.replace(
-            index.group(0), ""
-        ) + index.group(0).replace('[', '_').replace(']', '')
+            index.group(0), "") + index.group(0).replace('[', '_').replace(
+                ']', '')
 
     return normalized_name
 
@@ -124,8 +123,7 @@
 
 # $genblock$/vlog/tests/multiple_instance/multiple_instance.sim.v:12$64[57].\comb
 GENBLOCK_REGEX = re.compile(
-    "^\\$genblock\\$.*:[0-9]+\\$[0-9]+\\[(.*)\\]\\.\\\\(.*)"
-)
+    "^\\$genblock\\$.*:[0-9]+\\$[0-9]+\\[(.*)\\]\\.\\\\(.*)")
 
 
 def strip_name(name: str, include_index=True) -> str:
@@ -156,8 +154,8 @@
 
 
 def create_port(
-        dir_xml: ET.Element, cell_pin: CellPin, direction: str, metadata=None
-) -> ET.Element:
+        dir_xml: ET.Element, cell_pin: CellPin, direction: str,
+        metadata=None) -> ET.Element:
     cell_name, pin_name = cell_pin
     port = dict()
     port['name'] = pin_name
@@ -196,9 +194,7 @@
             assert avalue == dst[attr]
             raise ValueError(
                 '{} on net has value {} but pins have {}'.format(
-                    attr, dst[attr], avalue
-                )
-            )
+                    attr, dst[attr], avalue))
         dst[attr] = avalue
 
 
@@ -232,8 +228,8 @@
 
 
 def make_direct_conn(
-        ic_xml: ET.Element, driver: CellPin, sink: CellPin, path_attr: dict
-) -> ET.Element:
+        ic_xml: ET.Element, driver: CellPin, sink: CellPin,
+        path_attr: dict) -> ET.Element:
     dir_xml = ET.SubElement(ic_xml, 'direct')
     create_port(dir_xml, driver, "input")
     create_port(dir_xml, sink, "output")
@@ -244,8 +240,7 @@
             dir_xml, 'pack_pattern', {
                 'name': pack_name,
                 'type': 'pack'
-            }
-        )
+            })
         create_port(pp_xml, driver, "input")
         create_port(pp_xml, sink, "output")
 
@@ -255,8 +250,7 @@
             dir_xml, 'pack_pattern', {
                 'name': carry_name,
                 'type': 'carry'
-            }
-        )
+            })
         create_port(pp_xml, driver, "input")
         create_port(pp_xml, sink, "output")
 
@@ -265,19 +259,24 @@
 
 def make_mux_conn(
         ic_xml: ET.Element, mux_name: str, mux_inputs: Dict[CellPin, CellPin],
-        mux_outputs: Dict[CellPin, List[CellPin]]
-) -> ET.Element:
+        mux_outputs: Dict[CellPin, List[CellPin]]) -> ET.Element:
 
     mux_xml = ET.SubElement(ic_xml, "mux", {"name": mux_name})
 
     keys = sorted(list(mux_inputs.keys()))
-    for mux_input, driver in [(k, mux_inputs[k],) for k in keys]:
+    for mux_input, driver in [(
+            k,
+            mux_inputs[k],
+    ) for k in keys]:
         metadata = {'fasm_mux': '{}.{}'.format(mux_name, mux_input)}
         create_port(mux_xml, driver, "input", metadata=metadata)
 
     assert len(mux_outputs) == 1, mux_outputs
     keys = sorted(list(mux_outputs.keys()))
-    for mux_pin, sinks in [(k, mux_outputs[k],) for k in keys]:
+    for mux_pin, sinks in [(
+            k,
+            mux_outputs[k],
+    ) for k in keys]:
         assert len(sinks) == 1, sinks
         for sink_pin, path_attr in sinks:
             create_port(mux_xml, sink_pin, "output")
@@ -316,25 +315,20 @@
             drvs = mod.net_drivers(net)
             assert len(drvs) > 0, (
                 "ERROR: pin {}.{} has no driver, \
-                interconnect will be missing\n{}"
-                .format(cname, pin, mod)
-            )
+                interconnect will be missing\n{}".format(cname, pin, mod))
             assert len(drvs) < 2, (
                 "ERROR: pin {}.{} has multiple drivers, \
-                interconnect will be overspecified"
-                .format(cname, pin)
-            )
+                interconnect will be overspecified".format(cname, pin))
             for drv_cell, drv_pin in drvs:
                 net_attr = net_and_pin_attrs(
-                    yj, mod, (drv_cell, drv_pin), (pb_name, pin), net
-                )
+                    yj, mod, (drv_cell, drv_pin), (pb_name, pin), net)
 
                 drv_cell_name = strip_name(drv_cell)
                 assert drv_cell_name in valid_names
                 if drv_cell_name == mod_pname:
                     drv_cell_name = None
-                interconn[(drv_cell_name,
-                           drv_pin)].append(((pb_name, pin), net_attr))
+                interconn[(drv_cell_name, drv_pin)].append(
+                    ((pb_name, pin), net_attr))
 
         # Only consider outputs from cell to top level IO.
         # Inputs to other cells will be dealt with in those cells.
@@ -345,8 +339,7 @@
                 if sink_cell != mod.name:
                     continue
                 net_attr = net_and_pin_attrs(
-                    yj, mod, (pb_name, pin), (None, sink_pin), net
-                )
+                    yj, mod, (pb_name, pin), (None, sink_pin), net)
                 interconn[(pb_name, pin)].append(((None, sink_pin), net_attr))
 
     # Passthrough connections. Get ports along with connections
@@ -409,9 +402,21 @@
     interconn = {}
     for name, width, bits, iodir in mod.ports:
         if iodir == "input":
-            interconn[(None, name)] = [((mode_name, name,), {},)]
+            interconn[(None, name)] = [(
+                (
+                    mode_name,
+                    name,
+                ),
+                {},
+            )]
         else:
-            interconn[(mode_name, name)] = [((None, name,), {},)]
+            interconn[(mode_name, name)] = [(
+                (
+                    None,
+                    name,
+                ),
+                {},
+            )]
     return interconn
 
 
@@ -512,16 +517,14 @@
         return True
 
     assert '[' in v[0], "No index brackets found in item 0: {}\n{}".format(
-        v[0], v
-    )
+        v[0], v)
     list_name = v[0][:v[0].rfind('[')]
     sl = sorted(v, key=len)
     for i in range(0, len(v)):
         expected_item = "{}[{}]".format(list_name, i)
         assert expected_item == sl[
             i], "index {} expected: {} != actual: {}\n{}".format(
-                i, expected_item, sl[i], sl
-        )
+                i, expected_item, sl[i], sl)
     return list_name, len(v)
 
 
@@ -554,13 +557,11 @@
                 port_xml, 'pack_pattern', {
                     'name': carry_name,
                     'type': 'carry'
-                }
-            )
+                })
 
 
 def make_container_pb(
-        outfile, yj, mod, mod_pname, pb_type_xml, routing, children
-):
+        outfile, yj, mod, mod_pname, pb_type_xml, routing, children):
     # Containers have to include children
     # ------------------------------------------------------------
     for child_prefix, (child_type, children_names) in children.items():
@@ -598,8 +599,7 @@
             parent_xml.append(ET.Comment(comment_str))
 
         xmlinc.include_xml(
-            parent=parent_xml, href=pb_type_path, outfile=outfile, xptr=xptr
-        )
+            parent=parent_xml, href=pb_type_path, outfile=outfile, xptr=xptr)
 
     # Contains need interconnect to their children
     # ------------------------------------------------------------
@@ -631,8 +631,11 @@
         if driver_cell in routing_cells:
             continue
 
-        non_routing_sinks = [(sink, path_attr) for sink, path_attr in sinks
-                             if sink[0] not in routing_cells]
+        non_routing_sinks = [
+            (sink, path_attr)
+            for sink, path_attr in sinks
+            if sink[0] not in routing_cells
+        ]
 
         is_forking = len(non_routing_sinks) > 1
 
@@ -648,8 +651,7 @@
 
             make_direct_conn(
                 ic_xml, (normalize_pb_name(driver_cell), driver_pin),
-                (normalize_pb_name(sink_cell), sink_pin), attrs
-            )
+                (normalize_pb_name(sink_cell), sink_pin), attrs)
 
     # Generate the mux interconnects
     for mux_cell in routing_cells:
@@ -662,20 +664,17 @@
         assert len(mux_outputs) == 1, """\
 Mux {} has multiple outputs ({})!
 Currently muxes can only drive a single output.""".format(
-            mux_cell, ", ".join(mux_outputs.keys())
-        )
+            mux_cell, ", ".join(mux_outputs.keys()))
         for mux_output_pin, sinks in mux_outputs.items():
             assert len(sinks) == 1, """\
 Mux {}.{} has multiple outputs ({})!
 Currently muxes can only drive a single output.""".format(
-                mux_cell, mux_output_pin,
-                ", ".join("{}.{}".format(*pin) for pin, path_attr in sinks)
-            )
+                mux_cell, mux_output_pin, ", ".join(
+                    "{}.{}".format(*pin) for pin, path_attr in sinks))
             for (sink_cell, sink_pin), path_attr in sinks:
                 assert sink_cell not in routing_names, """\
 Mux {}.{} is trying to drive mux input pin {}.{}""".format(
-                    mux_cell, mux_output_pin, sink_cell, sink_pin
-                )
+                    mux_cell, mux_output_pin, sink_cell, sink_pin)
 
         mux_inputs = {}
         for (driver_cell, driver_pin), sinks in interconn.items():
@@ -690,8 +689,7 @@
 Pin {}.{} is trying to drive mux pin {}.{} (already driving by {}.{})\
                  """.format(
                     driver_cell, driver_pin, mux_cell, mux_pin,
-                    *mux_inputs[sink_pin]
-                )
+                    *mux_inputs[sink_pin])
                 mux_inputs[mux_pin] = (driver_cell, driver_pin)
 
         make_mux_conn(ic_xml, mux_cell, mux_inputs, mux_outputs)
@@ -744,8 +742,7 @@
                         "in_port": inport,
                         "out_port": port,
                         "max": str(atvalue)
-                    }
-                )
+                    })
             elif attr.startswith(dly_mat_prefix):
                 # Constant delay matrices
                 inp = attr[len(dly_mat_prefix):]
@@ -756,15 +753,18 @@
                         "in_port": inport,
                         "out_port": port,
                         "type": "max"
-                    }
-                )
+                    })
                 xml_mat.text = mat
 
 
 def make_pb_type(
-        infiles, outfile, yj, mod, mode_processing=False,
-        mode_xml=None, mode_name=None
-):
+        infiles,
+        outfile,
+        yj,
+        mod,
+        mode_processing=False,
+        mode_xml=None,
+        mode_name=None):
     """Build the pb_type for a given module. mod is the YosysModule object to
     generate."""
 
@@ -817,8 +817,7 @@
                 "num_pb": "1",
                 "name": mod_pname
             },
-            nsmap={'xi': xmlinc.xi_url}
-        )
+            nsmap={'xi': xmlinc.xi_url})
     else:
         pb_type_xml = ET.SubElement(
             mode_xml,
@@ -826,8 +825,7 @@
                 "num_pb": "1",
                 "name": mode_name
             },
-            nsmap={'xi': xmlinc.xi_url}
-        )
+            nsmap={'xi': xmlinc.xi_url})
 
     if 'blif_model' in pb_attrs:
         ET.SubElement(pb_type_xml, "blif_model",
@@ -874,9 +872,7 @@
                     flatten=False,
                     aig=False,
                     mode=smode,
-                    module_with_mode=mod.name
-                )
-            )
+                    module_with_mode=mod.name))
             mode_mod = mode_yj.module(mod.name)
 
             inter = {}
@@ -884,13 +880,13 @@
             # The mode has no children. Don't generate a pb_type then. Make
             # only the interconnect instead.
             if len(mode_mod.cells) == 0:
-                inter.update(get_interconnects(
-                    mode_yj, mode_mod, smode, [smode]))
+                inter.update(
+                    get_interconnects(mode_yj, mode_mod, smode, [smode]))
 
             # The mode has children, recurse
             else:
-                make_pb_type(infiles, outfile, mode_yj, mode_mod,
-                             True, mode_xml, smode)
+                make_pb_type(
+                    infiles, outfile, mode_yj, mode_mod, True, mode_xml, smode)
                 inter.update(mode_interconnects(mod, smode))
 
             # Add or update the interconnect.
@@ -901,9 +897,7 @@
             for (driv_cell, driv_pin), sinks in inter.items():
                 for (sink_cell, sink_pin), attrs in sinks:
                     make_direct_conn(
-                        ic_xml,
-                        (driv_cell, driv_pin),
-                        (sink_cell, sink_pin),
+                        ic_xml, (driv_cell, driv_pin), (sink_cell, sink_pin),
                         attrs)
 
     if not modes or mode_processing:
@@ -913,8 +907,7 @@
 
         if routing or children:
             make_container_pb(
-                outfile, yj, mod, mod_pname, pb_type_xml, routing, children
-            )
+                outfile, yj, mod, mod_pname, pb_type_xml, routing, children)
         else:
             make_leaf_pb(outfile, yj, mod, mod_pname, pb_type_xml)
 
@@ -926,8 +919,9 @@
     # Check Yosys version
     pfx = run.determine_select_prefix()
     if pfx != "=":
-        print("ERROR The version of Yosys found is outdated and not supported"
-              " by V2X")
+        print(
+            "ERROR The version of Yosys found is outdated and not supported"
+            " by V2X")
         sys.exit(-1)
 
     iname = os.path.basename(infiles[0])
@@ -946,9 +940,7 @@
             print(
                 "ERROR file name not of format %.sim.v ({}),"
                 " cannot detect top level. Manually specify"
-                " the top level module using --top".
-                format(iname)
-            )
+                " the top level module using --top".format(iname))
             sys.exit(1)
 
     top = top.upper()
@@ -958,8 +950,5 @@
     pb_type_xml = make_pb_type(infiles, outfile, yj, tmod)
 
     return ET.tostring(
-        pb_type_xml,
-        pretty_print=True,
-        encoding="utf-8",
-        xml_declaration=True
-    ).decode('utf-8')
+        pb_type_xml, pretty_print=True, encoding="utf-8",
+        xml_declaration=True).decode('utf-8')
diff --git a/v2x/yosys/json.py b/v2x/yosys/json.py
index b17ea1c..4159207 100755
--- a/v2x/yosys/json.py
+++ b/v2x/yosys/json.py
@@ -8,7 +8,6 @@
 # https://opensource.org/licenses/ISC
 #
 # SPDX-License-Identifier:	ISC
-
 """
 This is intended to provide a range of helper functions around the output of
 Yosys' `write_json`. Depending on the tasks, this may need to be flattened
@@ -28,8 +27,7 @@
 
     def __str__(self):
         return "YosysModule({},\n{})".format(
-            self.name, pprint.pformat(self.data)
-        )
+            self.name, pprint.pformat(self.data))
 
     @property
     def ports(self):
@@ -46,8 +44,7 @@
         plist = []
         for port, pdata in sorted(self.data["ports"].items()):
             plist.append(
-                (port, len(pdata["bits"]), pdata["bits"], pdata["direction"])
-            )
+                (port, len(pdata["bits"]), pdata["bits"], pdata["direction"]))
         return plist
 
     @property
@@ -90,8 +87,7 @@
     def nets(self):
         """List the net ids available in the design."""
         return list(
-            sorted(set(n['bits'][0] for n in self.data["netnames"].values()))
-        )
+            sorted(set(n['bits'][0] for n in self.data["netnames"].values())))
 
     def cell_type(self, cell):
         """Return the type of a given cell"""
@@ -240,8 +236,7 @@
                         conn_io.append(port)
                     else:
                         conn_io.append(
-                            "{}[{}]".format(port, pdata["bits"].index(net))
-                        )
+                            "{}[{}]".format(port, pdata["bits"].index(net)))
         return conn_io
 
     def conn_ports(self, net, pdir):
@@ -263,10 +258,8 @@
                         else:
                             conn_ports.append(
                                 (
-                                    cell,
-                                    "{}[{}]".format(port, condata.index(net))
-                                )
-                            )
+                                    cell, "{}[{}]".format(
+                                        port, condata.index(net))))
         return conn_ports
 
     def net_name(self, netid):
@@ -380,9 +373,7 @@
         if module not in self.data["modules"]:
             raise KeyError(
                 "No yosys module named {} (only have {})".format(
-                    module, self.data["modules"].keys()
-                )
-            )
+                    module, self.data["modules"].keys()))
         return YosysModule(module, self.data["modules"][module])
 
     def modules_with_attr(self, attr_name, attr_value):
diff --git a/v2x/yosys/run.py b/v2x/yosys/run.py
index 1a51dbd..92843a2 100755
--- a/v2x/yosys/run.py
+++ b/v2x/yosys/run.py
@@ -179,8 +179,7 @@
     infiles : list of input files
     """
     commands = "read_verilog {} {} {}; ".format(
-        get_defines(), get_includes(), " ".join(infiles)
-    ) + commands
+        get_defines(), get_includes(), " ".join(infiles)) + commands
     params = ["-p", commands]
     return get_output(params)
 
@@ -198,8 +197,7 @@
 
 
 def vlog_to_json(
-        infiles, flatten=False, aig=False, mode=None, module_with_mode=None
-):
+        infiles, flatten=False, aig=False, mode=None, module_with_mode=None):
     """
     Convert Verilog to a JSON representation using Yosys
 
@@ -309,8 +307,7 @@
     innet: Name of input net to find sinks of
     """
     return do_select(
-        infiles, module, "={} %co* =o:* %i ={} %d".format(innet, innet)
-    )
+        infiles, module, "={} %co* =o:* %i ={} %d".format(innet, innet))
 
 
 def list_clocks(infiles, module):
@@ -323,8 +320,7 @@
     """
     return do_select(
         infiles, module,
-        "=c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] =c:* %d =x:* %i"
-    )
+        "=c:* %x:+[CLK]:+[clk]:+[clock]:+[CLOCK] =c:* %d =x:* %i")
 
 
 def get_clock_assoc_signals(infiles, module, clk):
@@ -339,9 +335,7 @@
     return do_select(
         infiles, module,
         "select -list ={} %a %co* %x =i:* =o:* %u %i =a:ASSOC_CLOCK={} %u ={} "
-        "%d".
-        format(clk, clk, clk)
-    )
+        "%d".format(clk, clk, clk))
 
 
 # Find things which affect the given output
@@ -364,8 +358,7 @@
     clk: Name of clock to find associated signals
     """
     return do_select(
-        infiles, module, "select -list =w:*{} %a %co* =o:* %i".format(signal)
-    )
+        infiles, module, "select -list =w:*{} %a %co* =o:* %i".format(signal))
 
 
 def get_related_inputs_for_input(infiles, module, signal):
@@ -379,7 +372,6 @@
     """
     return [
         x for x in do_select(
-            infiles, module,
-            "select -list =w:*{} %a %co* %x =i:* %i".format(signal)
-        ) if x != signal
+            infiles, module, "select -list =w:*{} %a %co* %x =i:* %i".format(
+                signal)) if x != signal
     ]