<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <!-- https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#mixed-sequential-combinational-block -->
  <xi:include href="../dsp_combinational/dsp_combinational.model.xml" xpointer="xpointer(models/child::node())"/>
  <xi:include href="../fig42-dff/dff.model.xml" xpointer="xpointer(models/child::node())"/>
  <model name="DSP_PARTIAL_REGISTERED">
    <input_ports>
      <port name="a" combinational_sink_ports="out" clock="clk"/>
      <port name="b" combinational_sink_ports="out" clock="clk"/>
      <port name="clk" is_clock="1"/>
      <port name="m" combinational_sink_ports="out"/>
    </input_ports>
    <output_ports>
      <port name="out"/>
    </output_ports>
  </model>
</models>