)]}'
{
  "commit": "ec7600089b358ca9d77d30bed100b4bcc26d630c",
  "tree": "759dca75618570aff4bc31e088976ed5c44d4c26",
  "parents": [
    "9206adf8cb529ad66620ae894bf4ddcb4aaede09"
  ],
  "author": {
    "name": "Maciej Kurc",
    "email": "mkurc@antmicro.com",
    "time": "Thu Mar 05 12:02:05 2020 +0100"
  },
  "committer": {
    "name": "Maciej Kurc",
    "email": "mkurc@antmicro.com",
    "time": "Thu Mar 05 12:02:05 2020 +0100"
  },
  "message": "Addressed PR comments.\n\nSigned-off-by: Maciej Kurc \u003cmkurc@antmicro.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ec59b5c80372f3e2ca48714d5f8dd7d8ff6f73d5",
      "old_mode": 33188,
      "old_path": "tests/clocks/input_attr_not_clock/block.sim.v",
      "new_id": "f87f8b26d2ee8c1a5786ec44b56b35025a7341d5",
      "new_mode": 33188,
      "new_path": "tests/clocks/input_attr_not_clock/block.sim.v"
    },
    {
      "type": "modify",
      "old_id": "43831612fb19377e0bf055079e006914f8edaab9",
      "old_mode": 33188,
      "old_path": "v2x/yosys/utils.py",
      "new_id": "f6c3597cffd2f54112493aac8ca68e9aa8e82918",
      "new_mode": 33188,
      "new_path": "v2x/yosys/utils.py"
    }
  ]
}
