commit: 6b0f9f1e25b75e6cf5df0cc8d02489a08353eec6

[log]
author: Karol Gugala <kgugala@antmicro.com>

Tue May 21 15:40:57 2019 +0200
committer: Grzegorz Latosinski <glatosinski@antmicro.com>

Mon Nov 25 11:40:39 2019 +0100
tree: eef9be2dd002c667648232ccec9e381bf345d04e
parent: 312f8064793bb80b7ac83ce53345e358ef8c1cb8 [diff]

utils: timings: handle f7 and f8 mux timings

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

1 file changed

tree: eef9be2dd002c667648232ccec9e381bf345d04e

README.md

python-symbiflow-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.